Motorola DSP96002 - Manual (Page 32)

MOTOROLA DSP96002 USER’S MANUAL 3 - 9
All operations inside the Adder occur in one instruction cycle. Latches are provided on the Adder input op-
erand buses to avoid race conditions. The major components of the Adder are
• Add Unit
• Subtract Unit
• Barrel Shifter and Normalization Unit
• Exponent Comparator and Update Unit
• Special Function Unit
3.3.2.1 Add Unit
The Add Unit is a high speed 32-bit asynchronous adder used in all floating-point non-multiply operations
delivering a 32-bit result. The Add Unit performs automatic rounding to 32-bit result mantissa for the float-
ing-point add/subtract according to the IEEE Standard for single extended precision arithmetic. If rounding
to IEEE single precision is specified, the result is rounded to 24-bit mantissa according to the IEEE Stan-
dard for single precision arithmetic. The type of rounding is specified by the rounding mode bits in the MR
register.
Two input operands are received on two internal data buses which are the 32-bit mantissas and are sup-
plied to the Add Unit after the process of mantissa alignment required by a floating-point addition. The out-
put of the Add Unit is delivered to the rounding unit which produces the result that is stored in the destina-
tion register.
3.3.2.2 Subtract Unit
The Subtract Unit is a high speed 32-bit asynchronous adder/subtracter used in all floating-point non-mul-
tiply operations as well as all fixed-point operations delivering a 32-bit result. The Subtract Unit performs
automatic rounding to 32-bit result mantissa for the floating-point add/subtract according to the IEEE Stan-
dard for single extended precision arithmetic. If rounding to IEEE single precision is specified, the result is
rounded to 24-bit mantissa according to the IEEE Standard for single precision arithmetic. The type of
rounding is specified by the rounding mode bits in the MR register.
Two input operands are received on two internal data buses which are the 32-bit mantissas and are sup-
plied to the Subtract Unit after the process of mantissa alignment required by a floating-point subtraction.
For fixed-point operations the two input operands are supplied on the same data buses. The output of the
Subtract Unit is delivered, in case of floating-point operations, to the rounding unit.
The Subtract Unit delivers the result in the middle portion of the destination register in case of floating-point
operations and in the low portion of the destination register in case of integer operations.
3.3.2.3 Barrel Shifter and Normalization Unit
The Barrel Shifter is a 32-bit asynchronous parallel bidirectional (left-right) multibit shifter used in most float-
ing-point operations and in arithmetic and logical shifting operations delivering a 32-bit result. When used
in floating-point operations its main task is to provide operand alignment for add/subtract operations and
post normalization of the final result. When used in fixed-point shifts the Barrel Shifter performs the follow-
ing operations:
• single and multibit arithmetic shift left or right (ASL #n, ASR #n)
• single and multibit logical shift left or right (LSL #n, LSR #n)