Motorola DSP96002 - Manual (Page 18)

MOTOROLA DSP96002 USER’S MANUAL 2 - 15
The Port A/B bus control signals are designed for efficient interface to DRAM/VRAM devices in both ran-
dom read/write cycles and fast access modes such as those listed above. The bus control signal timing
is specified relative to the external clock (CLK) to enable synchronous control by an external state ma-
chine. An on-chip page circuit controls the
—
T
–
T pin, indicating to the external state machine when a slow
or fast access is being made. The page circuit operation and programming is described in Section seven.
4.11 BUS HANDSHAKE AND ARBITRATION
Bus transactions are governed by a single bus master. Bus arbitration determines which device becomes
the bus master. The arbitration logic implementation is system dependent, but must result in at most one
device becoming the bus master (even if multiple devices request bus ownership). The arbitration signals
permit simple implementation of a variety of bus arbitration schemes (e.g. fairness, priority, etc.). External
logic must be provided by the system designer to implement the arbitration scheme.
4.11.1 Bus Arbitration Signals
Four signals are provided for bus arbitration. Three of them are considered as local arbitration signals and
one as system arbitration signal. The local arbitration signals run between a potential bus master and the
arbitration logic. The local signals are
—
B
–
R,
—
B
–
G, and
—
B
–
A;
—
B
–
B is a system arbitration signal.
These signals are described below.
—
B
–
R Bus Request - Asserted by the requesting device to indicate that it wants to use the bus,
and is held asserted until it no longer needs the bus. This includes time when it is the
bus master as well as when it is not the bus master.
—
B
–
G Bus Grant - Asserted by the bus arbitration controller to signal the requesting device that
it is the bus master elect.
—
B
–
G is valid only when the bus is not busy (Bus Busy signal
described below).
—
B
–
A Bus Acknowledge - Asserted by the device (bus master) that received the bus owner-
ship from the bus arbitration controller. The master holds
—
B
–
A asserted for the dura-
tion of its bus possession.
—
B
–
A indicates whether the device is a bus master or a bus
slave. When asserted,
—
B
–
A indicates that the device is the bus master.
—
B
–
A may
be used as a three-state enable control for external address, data and bus control signal
buffers.
—
B
–
B Bus Busy - The system arbitration signal
—
B
–
B is monitored by all potential bus masters
and is derived from the local bus signal
—
B
–
A. This signal controls the hand-over of
bus ownership by the bus master at the end of bus possession. Typically
—
B
–
B is the
wired-OR of all bus acknowledgments.
—
B
–
B is asserted if the Bus Acknowledge signal
is asserted by the bus master.