Motorola DSP96002 - Manual (Page 800)

18 MOTOROLA
ANDI #$ef, OMR ; clear CE bit in OMR
NOP ; pipeline delay
NOP ; pipeline delay
NOP ; pipeline delay
PFLUSH
MOVEI #$04, OMR ; bootstrap from Port A
NOP ; pipeline delay
JMP #0 ; jump to bootstrap ROM
Notice that PFLUSH was fetched and executed in PRAM mode. It could have appeared
one cycle earlier, in which case it would have been fetched in cache mode but executed
in PRAM mode.
3 INTEGER MODE
The DSP96002’s integer performance has been doubled with the definition of the new in-
teger mode. The integer mode improves the performance of integer algorithms and sup-
ports
four new parallel integer operations that are enabled while the processor is in integer
mode:
• MPYS//ADD (integer signed multiply and add)
• MPYS//SUB (integer signed multiply and subtract)
• MPYU//ADD (integer unsigned multiply and add)
• MPYU//SUB (integer unsigned multiply and subtract).
A full description of these instructions appears in APPENDIX A on page 54. Since they
use the opcodes of the parallel floating-point instructions, the following four instructions
are disabled while the processor is in integer mode:
• FMPY//FADD.S
• FMPY//FSUB.S
• FMPY//FADD.X
• FMPY//FSUB.X