Motorola DSP96002 - Manual (Page 179)

MOTOROLA DSP96002 USER’S MANUAL 10 - 13
10.7.4 External Request During WAIT
Asserting
—
D
–
R when the chip is in the WAIT state (i. e., has executed a WAIT instruction) causes the chip
to exit the WAIT state and enter the Debug Mode. After receiving the acknowledge, the command controller
must negate
—
D
–
R . Note that in this case, the chip completes the execution of the WAIT instruction and
halts after the next instruction enters the instruction latch.
10.7.5 Software request during normal activity
Upon executing the (F)DEBUGcc instruction when the specified condition is true, the chip enters the Debug
Mode after the instruction following the (F)DEBUGcc instruction has entered the instruction latch (see the
DEBUGcc and FDEBUGcc instruction descriptions in Appendix A).
10.7.6 Enabling Trace Mode
When operating in Trace Mode and the Trace Counter has reached a value of zero, the chip enters the De-
bug Mode after completing the execution of the instruction that caused the last Trace Counter decrement.
Only instructions actually executed cause the Trace Counter to decrement i.e. a killed instruction will not
decrement the Trace Counter and will not cause the chip to enter the Debug Mode.
10.7.7 Enabling breakpoints
When operating in Trace Mode or in Normal Mode, and the breakpoint mechanism is enabled with a Break-
point Counter value of zero, the chip enters the Debug Mode after completing the execution of the instruc-
tion that caused the Breakpoint Counter decrement. In case of breakpoints on Program memory addresses,
the breakpoint will be acknowledged immediately after the execution of the instruction that has caused the
occurrence of the specified address. In case of breakpoints on Data memory addresses, the breakpoint will
be acknowledged after the completion of the instruction following the instruction that caused the occurrence
of the specified address.
10.8 PIPELINE INFORMATION
In order restore the pipeline to resume normal chip activity upon returning from the Debug Mode, a number
of on-chip registers store the chip pipeline status. Figure 10-7 illustrates a block diagram of Pipeline Infor-
mation Registers with the exception of the PAB registers which are shown in Figure 10-7.
10.8.1 PAB Registers (OPABF, OPABD)
There are two read only PAB registers which give pipeline information when the debug mode is entered.
The OPABF register tells which opcode address is in the fetch stage of the pipeline and OPABD tells which
opcode is in the decode stage. Under normal program flow conditions, the program address saved will be
that of the instruction preceding the last instruction fetched and decoded before the debug mode was en-
tered. The PAB registers can only be read or written through the serial interface.
10.8.2 PDB Register (OPDBR)
The PDB Register is a 32-bit latch that stores the value of the Program Data Bus generated by the last Pro-
gram Memory access of the core before the Debug Mode is entered. OPDBR can only be read or written