Motorola DSP96002 - Manual (Page 28)

MOTOROLA DSP96002 USER’S MANUAL 3 - 5
A program loop begins execution after the DO instruction and continues until the program address fetched
equals the loop address register contents (last address of program loop). The contents of the loop counter
are then tested for one. If the loop counter is not one, the loop counter is decremented and the top location
in the stack RAM is read (but not pulled) into the PC to return to the start of the loop. If the loop counter is
one, the program loop is terminated by incrementing the PC, reading the previous loop flag bit from the top
location in the stack into the status register, purging the stack (pulling the top location and discarding the
contents) and pulling the LA and LC registers off the stack and restoring the respective registers. When
terminating a loop the loop flag, LA and LC registers as well as the system stack pointer are restored.
3.2.8 Program Memory
The Program Memory consists of a 1,024 location by 32-bit RAM. Addresses are received from the pro-
gram control logic (usually the PC). The Program Memory may contain instructions, constants, and data
tables which are fixed at assembly time. The Program Memory is a dual-access memory in the sense that
it may be accessed twice during a cycle: once by the core and once by the DMA. Program Memory may
be expanded off-chip. Program RAM may be written to download instructions. The bootstrap ROM also ap-
pears in Program Memory space during the bootstrap mode. See Section 9.
3.2.9 External Bus Interfaces
The DSP96002 has two identical external bus interfaces. Each bus interface has a 32-bit wide address bus
and a 32-bit wide data bus, and may be used to access external Data Memory, Program Memory or I/O
devices. Separate select lines control access to the memory spaces. A Port Select control register permits
assigning sections of each memory space to each external bus interface port. Refer to Section 2 and Sec-
tion 9 for a detailed description of the external bus interface.
3.2.10 Internal Bus Switch and Bit Manipulation Unit
The Internal Bus Switch performs data transfers from one internal bus to another.
The Bit Manipulation Unit performs bit manipulation operations on memory and register operands on the
XDB, YDB, and GDB.
3.2.11 I/O Interfaces
The on-chip I/O interfaces are intended to minimize system chip count and "glue" logic in many DSP96002
applications. Each I/O interface has its own control, status and data registers and is treated as memory-
mapped I/O by the DSP96002. Each interface has several dedicated interrupt vector addresses and control
bits to enable/disable interrupts. This minimizes the overhead associated with servicing the device since
each interrupt source has its own service routine.
The DSP96002 provides the following I/O interfaces: two identical 32-bit parallel Host MPU/DMA Interface
peripherals are provided on the DSP96002, one connected to External Bus Interface A and the other to
External Bus Interface B; a two-channel DMA Controller.
3.2.11.1 Host Interfaces
The DSP96002 provides a Host MPU/DMA Interface for each of its external bus interface ports. Each Host
Interface (HI) is a 8-, 16-, 24- or 32-bit wide parallel port which may be connected directly to the data bus
of a host processor. The host processor may be any of a number of popular microcomputers or micropro-