Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 101)

DS4830A User’s Guide
101
Figure 11-5: Slave I
2
C Clock Stretching
Normally when the I
2
C slave controller is receiving data, the value of I2CACK is sent after the falling edge of the 8
th
clock. However, if clock stretching is enabled after the 8
th
clock, the I
2
C slave controller continues to output the
I2CACK bit until clock stretching is released by software. This allows software time to inspect data that is received
before responding with an appropriate acknowledge bit.
The applications should use clock stretching if the I
2
C slave interrupts are not assigned the highest priority. Generally
the application is set to respond only to interrupts from the I
2
C slave controller, thus not having to continuously poll
the slave I
2
C controller. After each byte transfer is complete, the I
2
C slave controller needs to either read the
received byte from I2CBUF_S or write the next byte to transmit to I2CBUF_S. Without using clock stretching, the
host can begin clocking the next byte before the I
2
C slave controller is prepared. A few conditions that may require
clock stretching to be enabled are listed below when used without RX FIFO and TX Pages.
• When a slave address match is made and the R/ W bit is set, the I 2
C slave controller is expected to transmit
a byte of data to the host. This byte of data needs to be written to I2CBUF_S. If clock stretching is not used,
software may not be able to write the correct data into I2CBUF_S prior to the first clock of the data byte.
• Following the transmission of data to the host, another byte may be requested by the host sending an ACK
bit. The I
2
C slave controller has to write next data to the I2CBUF_S prior to the first clock of the second byte
which sometimes may not be possible.
• After a byte is received by the I 2
C slave controller it may be necessary to stretch the clock. This allows
software to read the byte from I2CBUF_S and perform data processing.