Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 118)

DS4830A User’s Guide
118
12.5 – SPI Slave
The DS4830A has the following SPI interface signals.
FUNCTIONAL NAME EXTERNAL PIN NAME
SSPIDO: Output from serial shift register (MISO) GP6
SSPIDI: Input to serial shift register (MOSI) SDA
SSPICK: Serial shift clock from SPI master (SPICK) SCL
SSPICS: Slave select input (CS) GP7
12.5.1 – SPI Slave Select
The SPI Slave Select SSPICS can be configured to accept either an active low or active high signal via the Slave
Active Select Bit (SAS) in the SPI Configuration Register. The SAS bit allows the selection of SSPICS active state.
When SAS is cleared to 0, SSPICS is configured to be active low. When SAS is set to 1, SSPICS is configured to be
active high.
12.5.2 – SPI Transfer Baud Rates
When operating as a slave device, the SPI serial clock is driven by an external master. For proper slave operation,
the serial clock provided by the external master should not exceed the system clock frequency divided by 4.
12.5.3 – SPI Slave Operation
The SPI module operates in the slave mode when the MSTM bit is cleared to 0. In Slave mode, the SPI is dependent
on the SSPICK sourced from the master to control the data transfer.
The Slave Select SSPICS input must be externally asserted by a master before data exchange can take place.
SSPICS must be asserted before data transaction begin and must remain asserted for the duration of the
transaction. If data is to be transmitted by the slave device, it must be written to its shift register before the beginning
of a transfer cycle, otherwise the character already in the shift register will be transferred. The slave device considers
a transfer to begin with the first clock edge or the active SSPICS edge, dependent on the data transfer format. When
SAS is cleared to 0, the active SSPICS edge is the falling edge of SSPICS while if SAS is set to 1, the active
SSPCIS edge is the rising edge of SSPICS.
The SPI slave receives data from the external master SSPIDI pin, most significant bit first, while simultaneously
transferring the contents of its shift register to the master on the SSPIDO pin, also most significant bit first. Data
received from the external master replaces data in the internal shift register until the transfer completes. Just like in
the master mode of operation, received data is loaded into the read buffer and the SPI Transfer Complete flag is set
at the end of transfer. The setting of the Transfer Complete flag will generate an interrupt request if enabled. Note
also that when CKPHA=0, the most significant bit of the SPI data buffer will be shifted out on the 8
th shift clock edge.
When SSPICS is not asserted, the slave device ignores the SSPICK clock and the shift register is disabled. Under
this condition, the device is basically idle, no data is shifted out from the shift register and no data is sampled from
the SSPIDI pin. The SSPIDO pin is placed in an input mode and is weakly pulled high to allow other devices on the
bus to drive the bus. De-assertion of the SSPICS signal by the master during a transfer (before a full character, as
defined by CHR, is received) aborts the current transfer. When the transfer is aborted, no data is loaded into the read
buffer, the SPIC flag is not set, and the slave logic and the bit counter are reset.
In slave mode, the Clock Divider Ratio bits (CKR7:0) have no function since the serial clock is supplied by an
external master. The transfer format (CKPOL, CKPHA settings) and the character length selection (CHR) for the
slave device, however, should match the master for a proper communication.
Slave mode is used when the SPI is controlled by another peripheral device. The SPI is in slave mode when the
MSTM bit is cleared to logic 0.
Each SPI (named as SPI master or SPI slave in this section) can be used as either SPI master or Slave.