Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 49)

DS4830A User’s Guide
49
Table 7-1: ADC Configuration and Data Buffers
DATA BUFFER CONFIGURATION/DATA BUFFER SELECTION
0-15 External Channels (0-15 in single-ended or 0-7 in differential)
16 REFINA
17 REFINB
18 V DD (Supply Voltage)
19 DAC Internal Reference
20-21 Reserved, can be used with Location Override
22 Internal Die Temperature
23 Sample and Hold 0
24 Sample and Hold 1
0-24 (Any) ADC Internal Offset (with Location Override)
By default, the external channels GP0-15 are general-purpose inputs. The DS4830A has the Pin Select Register
(PINSEL) which is used to configure these external channels as analog pins for ADC or/and Quick Trip use. Each bit
location in this register corresponds to the ADC/QT input pin. The ADC controller uses a set of Special Function
Registers (SFRs) to configure the ADC for the desired mode of operation. The DS4830A ADC can operate in the
three modes mentioned below.
1. ADC Sequence Mode Conversions
2. Temperature Mode Conversions
3. Sample and Hold Mode Conversions
7.1.2 – ADC Conversion Sequencing
The DS4830A ADC controller performs a user defined sequence for up to 16 single-ended or 8 differential external
voltage channels. Additionally, the ADC controller allows the user to measure voltages of the DAC internal and
external references (REFINA and REFINB) and V
DD . The REFINA and REFINB can be used as analog channels
independent of DAC operation. Thus the DS4830A provides 18 analog channels for application usage. The ADC
controller provides 24 ADC internal configuration and averaging configuration registers. The configuration registers
are accessed by writing to the ADDATA register when ADST.ADCFG = 1 and ADST.ADCAVG = 0. The averaging
configuration registers are accessed by writing to the ADDATA register when ADST.ADCAVG = 1 and
ADST.ADCFG = 0. Each conversion in a sequence is setup using one of the ADC configuration and averaging
configuration registers. The results from the ADC converter are located in the 25 data buffers. These are accessed
by reading from the ADDATA register when ADST.ADCFG = 0 and ADST.ADCAVG = 0. See Figure 7-2 for ADC
configurations and data buffers.
The configuration register pointed to by ADDATA is selected using the ADIDX bits in the ADST register when
ADCFG = 1 and ADCAVG = 0. The individual configuration registers allows each of the conversions in a sequence
to select from the following options.
• ADC channel selection
• Differential or single-ended conversion
• Full scale range
• Extended acquisition enable
• ADC conversion data alignment (left or right)
• Alternate location
For more information, see the configuration register description for the ADDATA register.
A sequence is setup in the ADC Address register (ADADDR) by defining the starting conversion configuration
address (ADSTART) and an ending conversion configuration address (ADEND). The configuration start address
designates the configuration register to be used for the first conversion in a sequence. The configuration end
address designates the configuration register used for the last conversion in a sequence. A single channel
conversion can be viewed as a special case for sequence conversion, where the starting and ending configuration
address is the same. The configuration registers can be viewed as a circular register array where ADSTART does
not have to be less than ADEND. For example, if ADSTART = 1 and ADEND = 5, then the sequence of conversions
would be configurations 1, 2, 3, 4, 5. If ADSTART = 5 and ADEND = 1, then the sequence of conversions would be
configurations 5, 6, 7 . . . 23 , 0, 1.
The ADC has two conversion sequence modes, single and continuous which are set by the ADCONT bit. When the
start conversion bit (ADCONV) is set to ‘1’, the ADC controller starts the ADC conversion sequence. In single
sequence mode (ADCONT=0), the ADCONV bit remains set until the ADC has finished the conversion of the last
channel in the sequence. In continuous mode (ADCONT=1), the ADCONV bit remains set until the continuous mode