Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 102)

DS4830A User’s Guide
102
11.1.10 – SMBus Timeout
The I
2
C slave controller can also be used for SMBus or PMBus™ communication. To maintain SMBus compatibility,
a 30ms timer is implemented by the I
2
C slave controller. The purpose of this timer is to issue a timeout interrupt
when SCL is low for greater than 30ms. The timer only starts when none of the following conditions are true:
1. The I 2 C slave controller is in the idle state and there are no communications on the I 2 C bus. The timer should
not generate interrupts regardless of how long SCL is low.
2. The SMBUS mode bit is not set. This ensures the SMBUS timeout functionality does not interfere with
normal I
2
C functionality.
3. SCL is high. The timer is inactive whenever SCL is high. The timer is reset when it is inactive.
4. The I
2
C slave controller is disabled or used as a master I
2
C controller. The timer is not needed in this case.
The following description explains when the SMBus timer starts, assuming that all other START conditions are met.
When the I
2
C slave controller is idle and it receives a START, it exits the idle state and the timer becomes active
(starts counting) any time SCL goes low. If following the START, the master addresses a different slave on the bus,
the I
2
C slave controller is returned to the idle state and the timer is reset and becomes inactive. In short, as soon as
SCL goes low following a START, the SMBus timer becomes active until the I
2
C slave controller re-enters into idle
state.
When a timeout occurs, the timeout bit (I2CTOI) is set, which can generate an interrupt if enabled. If a timeout
occurs, it may be necessary to reset the I
2
C slave controller. See the Resetting the I
2
C Slave Controller section for
more details. SMBus mode selection is controlled by the SMB_MOD bit in I2CCN_S register. When the Slave
SMBus Mode Operation bit (SMB_MOD) is set to 1, the SMBUS timeout functionality is enabled.
11.1.11 – Resetting the I
2
C Slave Controller
The I
2
C Slave Controller can be reset by disabling the I
2
C Slave controller by writing ‘0’ at I2CEN bit in the I2CCN_S
register. A reset forces the I
2
C slave controller to release both SDA and SCL if they are being held low by the I
2
C
slave controller. The reset may reset few or all bits of I2CCN, I2CST and I2CBUF_S registers and reset the internal
state machine of the I
2
C slave controller. Following a reset, the I
2
C slave controller must be re-initialized.
Note: When the I
2
C slave interface is disabled, the I
2
C bootloader is not available.
PMBus is a trademark of SMIF, Inc.