Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 114)

DS4830A User’s Guide
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12.2.3 – Write Collision While Busy
A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY=1). Since
the shift register is single buffered in the transmit direction, writes to SPIB are made directly into the shift register.
Allowing the write to SPIB while another transfer is in progress could easily corrupt the transmit/receive data. When
such a write attempt is made, the current transfer continues undisturbed, the attempted write data is not transferred
to the shift register, and the control unit sets the Write Collision flag (SPICN.4: WCOL). Setting the WCOL bit to 1
causes an interrupt if SPI interrupt sources are enabled. Once set, the WCOL bit is cleared only by software or a
reset. Normally, write collisions are associated solely with slave devices since they do not control initiation of
transfers and do not have access to as much information about the SPICK clock as the master. As a master, write
collisions are completely avoidable, however, the control unit detects write collisions for both master and slave
modes.
12.3 – SPI Interrupts
Four flags in the SPICN SFR can generate an SPI interrupt when enabled.
• Mode Fault (MODF) – This is applicable in Master mode only.
• Write Collision (WCOL)
• Receive overrun
• SPI Transfer Complete
These four bits serve as interrupts flags that allow the system programmer to specify the source of interrupts which
may cause an interrupt request to the CPU. These bits default to 0 on reset and must be cleared by software when
set. Once the SPI Interrupt is enabled by setting the ESPII bit to ‘1’, any of the four SPI interrupt sources can cause
an interrupt.
12.4 – SPI Master
The DS4830A has the following SPI interface signals.
FUNCTIONAL NAME EXTERNAL PIN NAME
MSPIDI: Input to serial shift register (MISO) MDI
MSPIDO: Output from serial shift register (MOSI) MDIO
MSPICK: Serial shift clock sourced to slave device(s) (SPICK) MCL
MSPICS: (Optional) Mode fault detection input if enabled (MODFE=1) (SSEL) MCS
12.4.1 – SPI Transfer Baud Rates
When operating in the master mode, the SPI serial clock is sourced to the external slave device(s). The serial clock
baud rate is determined by the clock divide ratio specified in the SPI Clock Divider Ratio (SPICK) register. The SPI
module supports 256 different clock divide ratio selections for serial clock generation. The SPI Baud rate is
determined by the following formula:
12.4.2 – SPI Master Operation
The SPI module is placed in master mode by setting the Master Mode Enable (MSTM) bit in the SPI Control register
to 1. Only an SPI master device can initiate a data transfer. The master is responsible for manually
selecting/deselecting slave(s) via the MSPICS signal or any GPIO pin. Writing a data character to the SPI shift
register (SPIB) while in master mode starts a data transfer. The SPI master immediately shifts out the data serially
on the MSPIDO pin, most significant bit first, while providing the serial clock on MSPICK output. New data is
simultaneously received on the MSPIDI pin into the least significant bit of the shift register. The data transfer format
(clock polarity and phase), character length, and baud rate are all configurable as described earlier in the section.
During the transfer, the SPI Transfer Busy (SPICN.7:STBY) flag will be set to indicate that a transfer is in process. At
the end of the transfer, the data contained in the shift register is moved into the receive data buffer, the STBY bit is
cleared by hardware, and the SPI Transfer Complete flag (SPICN.6: SPIC) is set. Setting of the SPIC bit will
generate an interrupt request if SPI interrupt sources are enabled (ESPII=1).
The SPI master can be configured to transfer either 8 or 16 bits in an operation to accommodate network with
different word length requirements. The data transfer rate for the network is determined by the divider ratio in the
SPI Baud Rate =
Core Clock
2 * Clock Divide Ratio
where Clock Divider Ratio = (SPICK.7:0) + 1