Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 81)

DS4830A User’s Guide
81
SECTION 10 – I
2
C-COMPATIBLE MASTER INTERFACE
The DS4830A provides an I
2
C-compatible master controller that allows the DS4830A to communicate with a slave
device. The I
2
C master interface can be setup to provide system interrupts after each I
2
C event.
10.1 – Detailed Description
10.1.1 – Description of Master I
2
C Interface
The master I
2
C interface uses the MSDA and MSCL pins. These pins are the master I
2
C controller’s connection to
the SDA and SCL pins of an I
2
C bus. In addition to driving these pins, the I
2
C master port also senses the state of
both MSDA and MSCL. This allows the I
2
C master port to offer bus error detection and allows a slave device to clock
stretch.
Unless explicitly stated, all references to SDA and SCL in this section refer to the SDA and SCL lines of the I
2 C bus,
not the DS4830A’s I 2 C slave interface SDA and SCL pins.
10.1.2 – Default Operation
The I
2
C master controller is disabled by default. The I
2
C master controller is enabled by setting the I2CEN and
I2CMST bits in the I2CCN_M register to a 1. Prior to the I
2
C master controller being used for communication, some
software setup is required. This setup includes setting the clock rate, timeout period, and which I
2
C events should
generate interrupts. The DS4830A master I
2
C controller is not intended to be used on an I
2
C bus that has multiple
masters connected to the bus.
10.1.3 – I
2
C Clock Generation
In an I
2
C system, the master is responsible for generating the SCL signal. The DS4830A I
2
C Master Controller
provides complete control over the clock rate and duty cycle. The I
2
C Master Controller generates SCL from the
system clock. The bit rate is controlled by the I 2 C Clock Control Register (I2CCK_M).
The high period of SCL clock is defined by the high byte of the I
2 C Clock Control register (I2CCKH) whereas
the low period of SCL is defined by the low byte (I2CCKL). The minimum clock high period is three system clocks
while the minimum low period has to be at least five system clock periods. The I
2
C clock characteristics can be
defined by the following equations:
• SCL Low Time = System Clock Period x (I2CCKL[7:0] + 1)
• SCL High Time = System Clock Period x (I2CCKH[7:0] + 1)
• I 2
C Clock Rate = System Clock Frequency/(I2CCLK[7:0] + I2CCKH[7:0] + 2)
One feature of the master I
2
C controller is that it also monitors SCL while the clock is being output. This allows the
controller to ensure that the SCL level is at the desired level prior to beginning the count for SCL Low or High Time.
Figure 10-1 illustrates the SCL sampling performed by the master I
2
C controller. When SCL is released by the
master I
2
C controller, the rise time is determined by the capacitive loading and pullup resistance on the SCL line.
When the controller senses the SCL line has reached a high logic level, the count for SCL High Time is started. The
same is true for a falling edge. The SCL Low Time is only started after the controller senses the SCL line at a low
logic level.
Figure 10-1 also illustrates that the calculated I
2 C clock period is not exactly accurate because the rise and fall time
of SCL is not taken into consideration. The actual clock period will be the period set by the I2CCK_M register plus
any rise and fall time.