Section 24 – instruction set, Ds4830a user’s guide, Table 24-1. instruction set summary – Maxim Integrated DS4830A Optical Microcontroller User Manual

Page 203

Advertising
background image

DS4830A User’s Guide

203

SECTION 24 – INSTRUCTION SET

Table 24-1. Instruction Set Summary

MNEMONIC

DESCRIPTION

16-BIT INSTRUCTION

WORD

STATUS

BITS

AFFECTED

AP

INC/DEC

NOTES

LO

G

ICA

L O

P

E

R

A

T

IO

NS

AND src

Acc

 Acc AND src

f001 1010 ssss ssss

S, Z

Y

1

OR src

Acc

 Acc OR src

f010 1010 ssss ssss

S, Z

Y

1

XOR src

Acc

 Acc XOR src

f011 1010 ssss ssss

S, Z

Y

1

CPL

Acc

 ~Acc

1000 1010 0001 1010

S, Z

Y

NEG

Acc

 ~Acc + 1

1000 1010 1001 1010

S, Z

Y

SLA

Shift Acc left arithmetically

1000 1010 0010 1010

C, S, Z

Y

SLA2

Shift Acc left arithmetically twice

1000 1010 0011 1010

C, S, Z

Y

SLA4

Shift Acc left arithmetically four times

1000 1010 0110 1010

C, S, Z

Y

RL

Rotate Acc left (w/o C)

1000 1010 0100 1010

S

Y

RLC

Rotate Acc left (through C)

1000 1010 0101 1010

C, S, Z

Y

SRA

Shift Acc right arithmetically

1000 1010 1111 1010

C, Z

Y

SRA2

Shift Acc right arithmetically twice

1000 1010 1110 1010

C, Z

Y

SRA4

Shift Acc right arithmetically four times

1000 1010 1011 1010

C, Z

Y

SR

Shift Acc right (0

 msbit)

1000 1010 1010 1010

C, S, Z

Y

RR

Rotate Acc right (w/o C)

1000 1010 1100 1010

S

Y

RRC

Rotate Acc right (though C)

1000 1010 1101 1010

C, S, Z

Y

B

IT

O

P

E

RA

T

IO

NS

MOVE C, Acc.<b>

C

 Acc.<b>

1110 1010 bbbb 1010

C

MOVE C, #0

C

 0

1101 1010 0000 1010

C

MOVE C, #1

C

 1

1101 1010 0001 1010

C

CPL C

C

 ~C

1101 1010 0010 1010

C

MOVE Acc.<b>, C

Acc.<b>

 C

1111 1010 bbbb 1010

S, Z

AND Acc.<b>

C

 C AND Acc.<b>

1001 1010 bbbb 1010

C

OR Acc.<b>

C

 C OR Acc.<b>

1010 1010 bbbb 1010

C

XOR Acc.<b>

C

 C XOR Acc.<b>

1011 1010 bbbb 1010

C

MOVE dst.<b>, #1

dst.<b>

 1

1ddd dddd 1bbb 0111

C,E

2

MOVE dst.<b>, #0

dst.<b>

 0

1ddd dddd 0bbb 0111

C,E

2

MOVE C, src.<b>

C

 src.<b>

fbbb 0111 ssss ssss

C

MAT

H

ADD src

Acc

 Acc + src

f100 1010 ssss ssss

C, S, Z, OV

Y

1

ADDC src

Acc

 Acc + (src + C)

f110 1010 ssss ssss

C, S, Z, OV

Y

1

SUB src

Acc

 Acc – src

f101 1010 ssss ssss

C, S, Z, OV

Y

1

SUBB src

Acc

 Acc – (src + C)

f111 1010 ssss ssss

C, S, Z, OV

Y

1

B

RA

NCHIN

G

{L/S}JUMP src

IP

 IP + src or src

f000 1100 ssss ssss

6

{L/S}JUMP C, src

If C=1, IP

 (IP + src) or src

f010 1100 ssss ssss

6

{L/S}JUMP NC, src

If C=0, IP

 (IP + src) or src

f110 1100 ssss ssss

6

{L/S}JUMP Z, src

If Z=1, IP

 (IP + src) or src

f001 1100 ssss ssss

6

{L/S}JUMP NZ, src

If Z=0, IP

 (IP + src) or src

f101 1100 ssss ssss

6

{L/S}JUMP E, src

If E=1, IP

 (IP + src) or src

0011 1100 ssss ssss

6

{L/S}JUMP NE, src

If E=0, IP

 (IP + src) or src

0111 1100 ssss ssss

6

{L/S}JUMP S, src

If S=1, IP

 (IP + src) or src

f100 1100 ssss ssss

6

{L/S}DJNZ LC[n], src

If --LC[n] <> 0, IP

 (IP + src) or src

f10n 1101 ssss ssss

6

{L/S}CALL src

@++SP

 IP+1; IP  (IP+src) or src

f011 1101 ssss ssss

6,7

RET

IP

 @SP--

1000 1100 0000 1101

RET C

If C=1, IP

 @SP--

1010 1100 0000 1101

RET NC

If C=0, IP

 @SP--

1110 1100 0000 1101

RET Z

If Z=1, IP

 @SP--

1001 1100 0000 1101

RET NZ

If Z=0, IP

 @SP--

1101 1100 0000 1101

RET S

If S=1, IP

 @SP--

1100 1100 0000 1101

RETI

IP

 @SP-- ; INS 0

1000 1100 1000 1101

RETI C

If C=1, IP

 @SP-- ; INS 0

1010 1100 1000 1101

RETI NC

If C=0, IP

 @SP-- ; INS 0

1110 1100 1000 1101

RETI Z

If Z=1, IP

 @SP-- ; INS 0

1001 1100 1000 1101

RETI NZ

If Z=0, IP

 @SP-- ; INS 0

1101 1100 1000 1101

RETI S

If S=1, IP

 @SP-- ; INS 0

1100 1100 1000 1101

D

A

TA

TR

AN

SF

E

R

XCH

Swap Acc bytes

1000 1010 1000 1010

S

Y

XCHN

Swap nibbles in each Acc byte

1000 1010 0111 1010

S

Y

MOVE dst, src

dst

 src

fddd dddd ssss ssss

C,S,Z,E

(Note 8)

7,8

PUSH src

@++SP

 src

f000 1101 ssss ssss

7

POP dst

dst

 @SP--

1ddd dddd 0000 1101

C,S,Z,E

7

POPI dst

dst

 @SP-- ; INS  0

1ddd dddd 1000 1101

C,S,Z,E

7

CMP src

E

 (Acc = src)

f111 1000 ssss ssss

E

NOP

No operation

1101 1010 0011 1010

Note 1: The active accumulator (Acc) is not allowed as the src in operations where it is the implicit destination.
Note 2: Only module 8 and modules 0-5 are supported by these single-cycle bit operations. Potentially affects C or E if PSF register is the

destination. Potentially affects S and/or Z if AP or APC is the destination.

Note 3: The terms Acc and A[AP] can be used interchangeably to denote the active accumulator.

Advertising