Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 170)

DS4830A User’s Guide
170
21.2 – Debug Mode
There are two ways to enter the Debug Mode from Background Mode:
1. Issuance of the Debug command directly by the host via the TAP communication port, or
2. Breakpoint matching mechanism.
The host can issue the Debug background command to the debug engine. This direct Debug Mode entry is
nondeterministic. The response time varies dependent on system conditions when the command is issued. The
breakpoint mechanism provides a more controllable response, but requires that the breakpoints be initially
configured in Background mode. No matter the method of entry, the debug engine takes control of the CPU in the
same manner. Debug mode entry is similar to the state machine flow of an interrupt except that the target execution
address is x8010h which resides in the Utility ROM instead of the address specified by the IV register that is used for
interrupts. On debug mode entry, the following actions occur:
1. block the next instruction fetch from program memory
2. push the return address onto the stack
3. set the contents of IP to x8010h
4. clear the IGE bit to 0 to disable interrupt handler if it is not already clear.
5. halt CPU operation
Once in Debug mode, further breakpoint matches or host issuance of the Debug command are treated as no
operations and will not disturb debug engine operation. Entering debug mode also stops the clocks to all timers,
including the Watchdog Timer. Temporarily disabling these functions allows debug mode operations without
disrupting the relationship between the original user program code and hardware timed functions. No interrupt
request can be granted since the interrupt handler is also halted as a result of IGE = 0.
21.2.1 – Debug Mode Commands
The debug engine sets the data shift register status bits to 01b (debug-idle) to indicate that it is ready to accept
debug commands from the host.
The host can perform the following operations from debug mode:
• read register map
• read program stack
• read/write register
• read/write data memory
• single step of CPU (trace)
• return to background mode
• unlock password
The only operations directly controlled by the debug engine are single step and return. All other operations are
assisted by debug service routines contained in the Utility ROM. These operations require that multiple bytes be
transmitted and/or received by the host, however each operation always begins with host transmission of a
command byte. This command byte is decoded by the debug engine in order to determine the quantity, sequence,
and destination for follow-on bytes received from the host. Even though there is no timing window specified for
receiving the complete command and follow-on data, the debug engine must receive the correct number of bytes for
a particular command before executing that command. If command and follow-on data are transmitted out of byte
order or proper sequence, the only way to resolve this situation is to disable the debug engine by changing the
instruction register (IR2:0) and reloading the Debug instruction. Once the debug engine has received the proper
number of command and follow-on bytes for a given ROM assisted operation, it will respond with the following
actions:
• update the Command bits (CMD3:0) in the ICDC register to reflect the host request,
• enable the ROM if it is not been enabled,
• force a jump to ROM address x8010h, and
• set the data shift register status bits to 10b (debug-busy)
The ROM code performs a read to the ICDC register CMD3:0 bits to determine its course of action. Some
commands can be processed by the ROM without receiving data from the host beyond the initially supplied follow-on
bytes, while others (e.g., Unlock Password) require additional data from the host. Some commands need only to