Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 141)

DS4830A User’s Guide
141
15.2 – GPIO Port Register Descriptions
The DS4830A has 4 ports P0, P1, P2 and P6. Each port has 8 pins (exception is P6 which has 7 pin only). The
GPIO operation is to control/monitor through PDp, POp and PIp (p = 0, 1, 2 and 6). These ports are multiplexed with
various functions like ADC, DAC, Sample and Hold, PWM, I
2
C, 3-Wire, SPI etc. Additionally, these ports also provide
GPIO interrupts on all of the pins. A GPIO interrupt can be generated when the pin is being operated as a GPIO, or
a special. Three additional registers, EIFp, EIEp, and EIESp are used to control the GPIO interrupts.
On device reset, the TAP port is active, allowing for in-circuit debugging and programming. The JTAG is active by
default on Port6[3:0] and it is disabled when SC.TAP bit is set to ‘0’. Enabled special functions operate on the JTAG
ports only if SC.TAP bit is set to ‘0’. Port 6 also provides GPIO interrupts on all of the pins. The GPIO works only
when SC.TAP = 0. A GPIO interrupt can be generated when the pin is being operated as a GPIO, or a special or
alternate function. Three additional registers, EIF6, EIE6, and EIES6 are used to control the GPIO interrupts.
Port6.7 is not present in the Port6.
15.2.1 – GPIO Direction Register Port (PD0, PD1, PD2, and PD6)
Bit # 7 6 5 4 3 2 1 0
Name PDp_7 PDp_6 PDp_5 PDp_4 PDp_3 PDp_2 PDp_1 PDp_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
PDp is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is
independently controlled by its direction bit. When PDp.n (p = 0 to 7, n = 0 to 7) is set to ‘1’, the pin is an output; data
in the POp.n bit will be driven on the pin. When PDp.n is cleared to ‘0’, the pin is an input and allows an external
signal to drive the pin. Note that each port pin has a weak pullup circuit when functioning as an input. The P channel
pullup transistor is controlled by the POp.n bit. If POp.n is set to ‘1’, the corresponding weak pullup is turned on, if the
POp.n bit is cleared to ‘0’, the weak pullup is turned off and the pin’s input is high-impedance.
15.2.2 – GPIO Output Register Port (PO0, PO1, PO2, and PO6)
Bit # 7 6 5 4 3 2 1 0
Name POp_7 POp_6 POp_5 POp_4 POp_3 POp_2 POp_1 POp_0
Reset* 1 1 1 1 1 1 1 1
Access rw rw rw rw rw rw rw rw
*GPIO which are shared with DAC ports has POp.n = 0 on reset.
POp is an 8-bit register that controls the output data of a GPIO pin. If the pin is setup to be an output (PDp.n = 1),
the data in POp.n will be output on the pin. If the pin is set as an input (PDp.n = 0), setting POp.n to a ‘1’ enables a
p-channel weak pullup, otherwise the pin’s input is high impedance.
When the Port pins are operating as PWM pins, the data in POp will not affect PWM operation. Changing the
direction of the pin does not change the data content of POp.n.
15.2.3 – GPIO Input Register for Port (PI0, PI1, PI2, and PI6)
Bit #
7 6 5 4 3 2 1 0
Name PIp_7 PIp_6 PIp_5 PIp_4 PIp_3 PIp_2 PIp_1 PIp_0
Reset s s s s s s s s
Access r r r r r r r r
PIp is an 8-bit register which contains the data that is applied to the GPIO pins. The PIp input register contains valid
input data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical
states applied to the pins. Note that each pin has a weak pullup circuit when functioning as an input and the P
channel pullup transistor is controlled by the POp.n bit.
15.2.4 – GPIO Port External Interrupt Edge Select Register (EIES0, EIES1, EIES2, and EIES6)
Bit #
7 6 5 4 3 2 1 0
Name IESPp_7 IESPp_6 IESPp_5 IESPp_4 IESPp_3 IESPp_2 IESPp_1 IESPp_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
The EIESp register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge. Setting the
IESPp_n bits to 0 will trigger the corresponding interrupt on a positive edge. When these bits are set to a 1, the
interrupt will be on a negative edge.