DS4830A User’s Guide
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7.1.10 – ADC Data Reading .......................................................................................................................................... 54
7.1.11 – ADC Interrupts ................................................................................................................................................. 54
7.1.12 – ADC Internal Offset .......................................................................................................................................... 55
7.1.13 – DAC External Reference Pins (REFINA and REFINB) as ADC Channels ...................................................... 55
7.1.14 – Fast Conversion Mode (ADST.ENABLE_2X) .................................................................................................. 55
7.2 – ADC Register Descriptions ....................................................................................................................................... 56
7.2.1 – ADC Control Register (ADCN) ........................................................................................................................... 56
7.2.2 – ADC Status Register (ADST) ............................................................................................................................. 57
7.2.3 – PIN Select Register (PINSEL) ........................................................................................................................... 57
7.2.4 – ADC Status Register (ADST1) .......................................................................................................................... 58
7.2.5 – ADC Address Register (ADADDR) .................................................................................................................... 58
7.2.6 – ADC Data and Configuration Register (ADDATA) ............................................................................................. 58
7.2.7 – Reference Pin Configuration Register (RPCFG) ............................................................................................... 60
7.2.8 – Temperature Control Register (TEMPCN) ....................................................................................................... 61
7.2.9 – Average and Reference Control Register (REFAVG) ..................................................................................... 61
7.2.10 – ADC Voltage Offset Register (ADVOFF) ......................................................................................................... 62
7.2.11 – ADC Voltage Scale Trim Registers (ADCG1, ADCG2, ADCG3 and ADCG4) ................................................ 62
7.3 – ADC Code Examples ................................................................................................................................................ 63
SECTION 8 – SAMPLE AND HOLD ..................................................................................................................................... 65
8.1 – Detailed Description ................................................................................................................................................. 65
8.1.1 – Operation ........................................................................................................................................................... 65
8.1.2 – Fast Mode Operation ......................................................................................................................................... 66
8.1.3 – Sampling Control ............................................................................................................................................... 67
8.1.4 – Pin Capacitance Discharge ............................................................................................................................... 68
8.1.5 – Sample and Hold Data Reading ........................................................................................................................ 69
8.1.6 – Sample and Hold Interrupts ............................................................................................................................... 69
8.2 – Sample and Hold Register Descriptions ................................................................................................................... 70
SECTION 9 – QUICK TRIP (FAST COMPARATOR) ........................................................................................................... 73
9.1 – Detailed Description ................................................................................................................................................. 73
9.1.1 – Quick Trip List Sequencing ................................................................................................................................ 74
9.1.2 – Operation ........................................................................................................................................................... 74
9.1.3 – Setting Quick Trip Thresholds ........................................................................................................................... 75
9.1.4 – Quick Trip Interrupts .......................................................................................................................................... 76
9.2 – Quick Trip Register Descriptions .............................................................................................................................. 77
SECTION 10 – I
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C-COMPATIBLE MASTER INTERFACE .................................................................................................. 81
10.1 – Detailed Description ............................................................................................................................................... 81
10.1.1 – Description of Master I
C Interface .................................................................................................................. 81
10.1.2 – Default Operation ............................................................................................................................................. 81
10.1.3 – I
C Clock Generation ....................................................................................................................................... 81
10.1.4 – Timeout ............................................................................................................................................................ 82
10.1.5 – Generating a START ....................................................................................................................................... 83
10.1.6 – Generating a STOP ......................................................................................................................................... 85
