14 – command 21h – dump data, 15 – command 30h – crc code, 16 – command 31h – crc data – Maxim Integrated DS4830A Optical Microcontroller User Manual
Page 188
DS4830A User’s Guide
188
22.3.14 – Command 21h – Dump Data
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 5
Byte 6
Length
Bytes
Byte
Length+7
Command
Data In
Data In
Data In
Data In
Data In
NOP
Data Out
Return
Input
21h
2
AddrL
AddrH
LengthL
LengthH
00h
00h
00h
Output
X
X
X
X
X
X
X
Memory
3Eh
This command returns the contents of the SRAM memory. The memory dump begins at byte address AddrH:AddrL
and will contain LengthH:LengthL bytes. This command is password protected.
22.3.15 – Command 30h – CRC Code
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte
7
Byte 8
Byte 9
Byte
10
Command Data In
Data In Data In
Data In
Data In
NOP
Data
Out
Data
Out
Return
Input
30h
2
AddrL
AddrH
LengthL LengthH
00h
00h
00h
00h
Output
X
X
X
X
X
X
X
CRCL
CRCH
3Eh
This command returns the CRC-16 value (CRCH:CRCL) of the (LengthH:LengthL) bytes of program flash starting at
(AddrH:AddrL). The formula for the CRC calculation is X
16
+ X
15
+ X
2
+ 1. This command is password protected.
The CRC calculation takes approximately 45 system clock cycles per byte (4.5µs/byte). During this time polling
should be performed to determine when the loader has finished executing the CRC calculation. If using the I
2
C
loader, user should wait for time according to given length and read CRCL, CRCH, 3Eh. If using the JTAG loader,
the JTAG status bits can be used to determine when the CRC calculation is complete.
22.3.16 – Command 31h – CRC Data
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte
7
Byte 8
Byte 9
Byte
10
Command Data In
Data In Data In
Data In
Data In
NOP
Data
Out
Data
Out
Return
Input
31h
2
AddrL
AddrH
LengthL LengthH
00h
00h
00h
00h
Output
X
X
X
X
X
X
X
CRCL
CRCH
3Eh
This command returns the CRC-16 value (CRCH:CRCL) of the (LengthH:LengthL) bytes of data memory starting at
(AddrH:AddrL). The formula for the CRC calculation is X
16
+ X
15
+ X
2
+ 1. This command is password protected.
The CRC calculation takes approximately 45 system clock cycles per byte (4.5µs/byte). During this time polling
should be performed to determine when the loader has finished executing the CRC calculation. If using the I
2
C
loader, user should wait for time according to given length and read CRCL, CRCH, 3Eh. If using the JTAG loader,
the JTAG status bits can be used to determine when the CRC calculation is complete.