1 – servicing interrupts, Ds4830a user’s guide – Maxim Integrated DS4830A Optical Microcontroller User Manual
Page 41
DS4830A User’s Guide
41
Note: Some of the DS4830A module and peripheral interrupts sources are shown in the Figure 5-1 interrupt
hierarchy diagram. See the corresponding sections of this user’s guide for more detailed information about all of the
possible interrupts.
5.1 – Servicing Interrupts
For the DS4830A to service an interrupt, interrupts must be enabled locally, modularly, and globally. The Interrupt
Global Enable (IGE) bit is located in the Interrupt Control (IC) register acts as a global interrupt mask. This bit
defaults to 0, and it must be set to 1 before any interrupt takes place.
The local interrupt-enable bit for a particular source is in one of the peripheral registers associated with that
peripheral module, or in a system register for any system interrupt source. Between the global and local enables are
intermediate per-module and system interrupt mask bits. These mask bits reside in the Interrupt Mask system
register. By implementing intermediate per-module masking capability in a single register, interrupt sources spanning
multiple modules can be selectively enabled/disabled in a single instruction. This promotes a simple, fast, and user-
definable interrupt prioritization scheme. The interrupt source-enable hierarchy is illustrated in Figure 5-1 as well as
Table 5-1.
Table 5-1: Interrupt Sources and Control Bits
INTERRUPT
INTERRUPT FLAG
LOCAL ENABLE BIT
MODULE
INTERRUPT
IDENTIFICATI
ON BIT
INTERRUPT
IDENTIFICATION
BIT
MODULE
ENABLE
BIT
External Interrupt Pp.n
(here p = 0,1,2 and n = 0 to 7)
EIFp.IEn
EIEp.EXn
-
IIR.II0
IMR.IM0
Timer1 Interrupt
GTCN1.GTIF
GTCN1.GTIE
-
External Interrupt Pp.n
(here p = 6 and n = 0 to 6)
EIFp.IEn
EIEp.EXn
MIIR1.Pp_n
IIR.II1
IMR.IM1
Supply Voltage Monitor Interrupt
SVM.SVMI
SVM.SVMIE
MIIR1.SVM
I
2
C Master Start Interrupt
I2CST_M.I2CSRI
I2CIE_M.I2CSRIE
MIIR1.I2CM
I
2
C Master Transmit Complete
Interrupt
I2CST_M.I2CTXI
I2CIE_M.I2CTXIE
I
2
C Master Receive Ready Interrupt
I2CST_M. I2CRXI
I2CIE_M.I2CRXIE
I
2
C Master Clock Stretch Interrupt
I2CST_M.I2CSTRI
I2CIE_M.I2CSTRIE
I
2
C Master Timeout Interrupt
I2CST_M.I2CTOI
I2CIE_M.I2CTOIE
I
2
C Master NACK Interrupt
I2CST_M.I2CNACKI
I2CIE_M.I2CNACKIE
I
2
C Master Receiver Overrun Interrupt
I2CST_M.I2CROI
I2CIE_M.I2CROIE
I
2
C Master Stop Interrupt
I2CST_M.I2CSPI
I2CIE_M.I2CSPIE
I
2
C Slave Start Interrupt
I2CST_S.I2CSRI
I2CIE_S.I2CSRIE
-
IIR.II2
IMR.IM2
I
2
C Slave Transmit Complete Interrupt
I2CST_S.I2CTXI
I2CIE_S.I2CTXIE
I
2
C Slave Receive Ready Interrupt
I2CST_S. I2CRXI
I2CIE_S.I2CRXIE
I
2
C Slave Clock Stretch Interrupt
I2CST_S.I2CSTRI
I2CIE_S.I2CSTRIE
I
2
C Slave Timeout Interrupt
I2CST_S.I2CTOI
I2CIE_S.I2CTOIE
I
2
C Slave Address Match Interrupt
I2CST_S.I2CAMI
I2CIE_S.I2CAMIE
I
2
C Slave NACK Interrupt
I2CST_S.I2CNACKI
I2CIE_S.I2CNACKIE
I
2
C Slave General Call Interrupt
I2ST_S.I2CGCI
I2CIE_S.I2CGCIE
I
2
C Slave Receiver Overrun Interrupt
I2CST_S.I2CROI
I2CIE_S.I2CROIE
I
2
C Slave Stop Interrupt
I2CST2_S.I2CSPI
I2CIE2_S.I2CSPIE
I
2
C Slave Start Address Interrupt
I2CST2_S.SADI
I2CIE2_S. SADIE
I
2
C Slave Memory Address Interrupt
I2CST2_S.MADI
I2CIE2_S. MADIE
I
2
C Slave Page Threshold Interrupt
I2CTXFST.THSH
I2CTXFIE.THSH
I
2
C Slave FIFO Threshold Interrupt
I2CRXFST.THSH
I2CRXFIE.THSH
Timer2 Interrupt
GTCN1.GTIF
GTCN1.GTIE
-
IIR.II3
IMR.IM3
Software Interrupts
SW.Fn
(n = 0,1,2,3)
-
-
ADC Data Available Interrupt
ADST1.ADDAI
ADCN.ADDAIE
MIIR4.ADC
IIR.II4
IMR.IM4
Internal Temperature Interrupt
ADST1.INTDAI
TEMPCN.INT_IEN
Sample and Hold 0 Interrupt
ADST1.SH0DAI
SHCN.SHDAI0_EN
Sample and Hold 1 Interrupt
ADST1.SH1DAI
SHCN.SHDAI1_EN
3- Wire Interrupt
TWR.TWI
TWR.TWIE
MIIR4.TW
SPI Slave Transfer Complete
SPICN_S.SPIC
SPICF_S.ESPII
MIIR4.SPI_S
SPI Slave Write Collision
SPICN_S.WCOL
SPI Slave Receive Overrun
SPICN_S.ROVR