Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 95)

DS4830A User’s Guide
95
11.1 – Detailed Description
The I
2
C slave controller has two different modes that can be used to transmit and receive data. The first option
transmits and received data one byte at a time. An advanced mode uses 8-byte buffers for transmiting and receiving
data, which is enabled by setting the TXPG_EN bit in the I2CTXFIE and the FIFO_EN bit in the I2CRXFIE registers.
Using this advanced mode of operation, the DS4830A can support 400kHz I
2
C operation without clock stretching.
11.1.1 – Default Operation
The I
2
C slave controller is enabled (I2CCN_S.I2CEN=1) by default. As long as the I
2
C slave controller is enabled, the
DS4830A I 2 C bootloader can operate. This allows bootloading of blank devices without any setup of the I 2 C slave
controller. Prior to the I 2 C slave controller being used for normal data communication, the I 2 C SFRs should be
configured for necessary I
2
C communication. These configurations include setting an I
2
C slave address and enabling
the slave controller to generate interrupts during I
2
C events. This controller can also operate as an SMBUS slave.
11.1.2 – Slave Addresses
Prior to communication, an I
2
C slave address may need to be selected. By default, the I
2
C slave controller normally
responds to two slave addresses. The I
2
C bootloader uses address 34h. This bootloader address cannot be changed
and should not be used as the device slave address for normal communication. The second slave address (default
address 36h) is the address used for communication with the host. This slave address can be programmed by
writing the desired slave address to the I2CSLA_S register. The address contained in the I2CSLA_S register is the
address with the R/
W bit. If an address other than 36h is desired, the I2CSLA_S register can be programmed with
this new address.
The DS4830A has three more user-programmable slave addresses that can be programmable using the
I2CSLA2_S, I2CSLA3_S, and I2CSLA4_S registers, respectively. By default, these slave addresses are disabled
and can be individually enabled by writing ‘1’ to the ADDR2EN, ADDR3EN, and ADDR4EN bits, which are defined in
the I2CCN_S register.
The I
2
C slave controller supports the General Call Address, which is 00h with the I2CSLA_S slave register. This
feature can be enabled by setting the I2CCN_S.I2CGCEN bit to a 1.
11.1.3 – I
2
C START Detection
The I
2
C Slave Controller always monitors the I
2
C bus for an I
2
C START, which is a high to low transition on SDA
while SCL is held high. If an I
2
C START (or restart) condition is detected, the I
2
C slave sets the I2CSRI bit in the
I2CST_S register, which can cause an interrupt if enabled. The detection of a START brings the I 2 C controller out of
its idle state. Following a START, the I 2 C controller begins to monitor data on the I 2 C bus and the I2CBUSY bit is set
to a 1. The I2CBUS bit is also set to a 1 to indicate that the I 2 C bus is currently busy.
11.1.4 – I
2 C STOP Detection
The I
2
C Slave Controller also always monitors the I
2
C bus for an I
2
C STOP, which is a low to high transition on SDA
while SCL is held high. If an I
2
C STOP condition is detected, the I
2
C slave controller sets the I2CSPI bit in the
I2CST_S register, which can cause an interrupt if enabled. The I2CBUS bit is cleared to 0 following a STOP to
indicate that the I
2
C bus is no longer busy.
11.1.5 – Slave Address Matching
Following an I
2
C START or restart, the I
2
C slave controller knows that the next byte of data to be transmitted by the
host should be the slave address. The I
2
C slave automatically monitors for the slave address without any software
interaction. The I
2
C slave controller compares the first 7 bits received to the slave address programmed in the
I2CSLA_S register. It also compares the first 7 bits received to the slave addresses programmed in the I2CSLA2_S,
I2CSLA3_S, and I2CSLA4_S registers, if they are enabled. If the received slave address matches with one of
enabled I
2 C Slave addresses, the I 2 C slave controller does the following steps. This is illustrated in Figure 11-2
(without RX FIFO and TX Pages) and Figure 11-4 (with RX FIFO and TX Pages).
• Transmit an ACK or NACK on the 9 th
clock based upon the setting of the I2CCN_S.I2CACK bit.
• Set the matched slave address I2CMODE bit with the value of the received R/ W bit. This bit can be used by
software to determine if the I
2
C slave controller should receive or transmit data.
• Sets the I2CST_S.I2CAMI bit to indicate that a slave address match was made. The setting of this bit can
generate an interrupt if enabled. Additionally, the I
2
C slave controller sets following values in SLA [3:0] bits in
CUR_SLA register according to the matched slave address.