Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 13)

DS4830A User’s Guide
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SECTION 2 – ARCHITECTURE
The DS4830A contains a low-cost, high-performance microcontroller with flash memory. It is structured on a highly
advanced, 16-accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle
without pipelining, since the instruction contains both the opcode and data. The highly efficient core is supported by 16
accumulators and a 32-level hardware stack, enabling fast subroutine calling and task switching.
Data can be quickly and efficiently manipulated with three internal data pointers. Two of these data pointers, DP0 and
DP1, are stand-alone 16-bit pointers. The third data pointer, Frame Pointer, is composed of a 16-bit base pointer (BP) and
an 8-bit offset register (OFFS). All three pointers support post-increment/decrement functionality for read operations and
pre-increment/decrement for write operations. For the Frame Pointer (FP=BP[OFFS]), the increment/decrement operation
is executed on the OFFS register and does not affect the base pointer. Multiple data pointers allow more than one
function to access data memory without having to save and restore data pointers each time.
Stack functionality is provided by dedicated memory with a 16-bit width and a depth of 32. An on-chip memory
management unit (MMU) allows logical remapping of the program and data spaces, and thus facilitates in-system
programming and fast access to data tables, arrays, and constants located in flash memory.
This section provides details on the following topics.
1. Instruction decoding
2. Register space
3. Memory types
4. Program and data memory mapping and access
5. Data alignment
6. Reset conditions
7. Clock generation
2.1 – Instruction Decoding
The DS4830A uses the standard 16-bit core instruction set, which is described in the Instruction Set section. Every
instruction is encoded as a single 16-bit word. The instruction word format is shown in Figure 2-1.
FORMAT DESTINATION SOURCE
s s d f s s s s s s d d d d d d
Figure 2-1: Instruction Word Format
• Bit 15 (f) indicates the format for the source field of the instruction as follows:
o If f equals 0, the instruction is an immediate source instruction. The source field represents an immediate
8-bit value.
o If f equals 1, the instruction is a register source instruction. The source field represents the register that
the source value will be read from.
• Bits 14 to 8 (ddddddd) represent the destination for the transfer. This value always represents a destination
register. The lower four bits contain the module specifier and the upper three bits contain the register index in
that module.
• Bits 7 to 0 (ssssssss) represent the source for the transfer. Depending on the value of the format field, this can
either be an immediate value or a source register. If this field represents a register, the lower four bits contain the
module specifier and the upper four bits contain the register index in that module.
This instruction word format presents the following limitations.
1. There are 32 registers per register module, but only four bits are allocated to designate the source register and
only three bits are allocated to designate the destination register.
2. The source field only provides 8 bits of data for an immediate value; however a 16-bit immediate value may be
required.
The DS4830A uses a prefix register (PFX) to address these limitations. The prefix register provides the additional bits
required to access all 32 register within a module. The prefix register also provides the additional 8 bits of data required
to make a 16-bit immediate data source. The data that is written to the prefix register survives for only one clock cycle.
This means the write to the prefix register must occur immediately prior to the instruction requiring the prefix register. The
prefix register is cleared to zero after one cycle so it will not affect any other instructions. The write to the prefix register is