Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 60)

DS4830A User’s Guide
60
7.2.6.2 – ADC Average Register (ADDATA when ADCAVG = 1 and ADCFG = 0)
When ADCAVG = 1 and ADCFG = 0, writing to the ADDATA register writes to one of the averaging configuration
registers. The averaging configuration register written to is selected by the ADIDX[1:0] bits. The ADIDX[1:0] bits are
automatically incremented after a write to ADDATA. This allows consecutive writes of ADDATA to setup consecutive
average registers. The average registers are reset to ‘0’ on all forms of reset.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name - - - - - - - - - - - - - - AVG[1:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r r r r r r r r r r r r r r rw* rw*
* When ADCAFG = 1, unrestricted read, but can only be written to when ADCONV = 0.
BIT
NAME DESCRIPTION
15:2 - Reserved. The user should not write to these bits.
1:0 AVG[1:0] ADC Average Select: These bits select number of ADC samples to be averaged by the
ADC controller.
AVG[1:0] Samples Average
00 1
01 4
10 8
11 16
7.2.6.3 – ADC Data Buffer (ADDATA when ADCFG = 0 and ADCAVG = 0)
When ADCFG = 0 and ADCAVG = 0, reading from the ADDATA register reads the ADC results stored in one of the
25 data buffers. The ADIDX[4:0] bits point to the data buffer to be read. Reading ADDATA register returns the 14-bits
(13 bits plus a sign bit) of ADC conversion data from the selected data buffer memory. The ADIDX[4:0] bits are
automatically incremented after a read of ADDATA. This allows multiple reads of ADDATA to access consecutive
data buffer locations without needing to change the ADIDX[4:0] bits. The data buffers are reset to 0 on all forms of
reset and are not writable by the user.
The data that is read from the ADC Buffer may be from either a temperature or voltage conversion. Also, the data
may be right or left aligned. Table 7-4 shows the returned bit weighting for each type of conversion.
Table 7-4: Voltage Data (ADC and Sample and Hold) and Temperature Bit Weighting with Alignment Option
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Temperature Right Aligned S S S 2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
Temperature Left Aligned S 2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
0 0
Voltage Right Aligned S S S 2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Voltage Left Aligned S 2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
0 0
The ADC controller produces temperature, sample and hold and ADC data reading in the 2’s complement format.
7.2.7 – Reference Pin Configuration Register (RPCFG)
See Section 6.2.3 – Reference Pin Configuration Register (RPCFG) for detailed information about RPCFG SFR.