Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 150)

DS4830A User’s Guide
150
The specified hardware multiplier operation begins when the final operand(s) is loaded and will complete in a single
cycle. The read-only MC1R, MC0R result registers can be accessed in the very next cycle unless
accumulation/subtraction with MC2:0 is requested (MCW = 0 and MMAC = 1), in which case, one cycle is required
so that stable data can be read. When MCW = 0, the MC2:0 registers always require one wait cycle before the
operation result is accessible. The single wait cycle needed for updating the MC2:0 registers with a calculated result
does not prevent initiating another calculation. Back-to-back operations can be triggered (independent of data type
and operand count) without the need of wait state between the loadings of operands.
Table 18-1 Hardware Multiplier
Operations
MCW:MSUB:MMAC OPERATION MC2 MC1 MC0 MC1R:MC0R OF STATUS
000 Multiply MA*MB MA*MB No
001 Multiply-Accumulate MC+(MA*MB) 32lsbits of (MC+2*(MA*MB)) Yes
010 Multiply-Negate (SUS = 0 only) -(MA*MB) -(MA*MB) No
011 Multiply-Subtract MC-(MA*MB) 32lsbits of (MC-2*(MA*MB)) Yes
100 Multiply MC2 MC1 MC0 MA*MB No
101 Multiply-Accumulate MC2 MC1 MC0 32lsbits of (MC+(MA*MB)) No
110 Multiply-Negate (SUS = 0 only) MC2 MC1 MC0 -(MA*MB) No
111 Multiply-Subtract MC2 MC1 MC0 32lsbits of (MC-(MA*MB)) No
The DS4830A has two sets of internal MAC registers to allow interruptible MAC operation. The MACRSEL bit in the
MACSEL register selects one of the MAC registers.
Internal Registers
MCNT0
MA0
MB0
MC0_0
MC2_0
MC1_0
MC0R_0
MC1R_0
MUX
MAC
CORE
MACRSEL
MCNT1
MA1
MB1
MC0_1
MC2_1
MC1_1
MC0R_1
MC1R_1
MCNT
MA
MB
MC0
MC2
MC1
MC0R
MC1R
MAC SFRs
Figure 18-2: Dual MAC Registers Organization