Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 14)

DS4830A User’s Guide
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done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute in
a single cycle, two cycles are needed for instructions that require the prefix register.
The architecture of the DS4830A is transport-triggered. This means that writing to or reading from certain register
locations will also cause side effects to occur. These side effects form the basis of the DS4830A’s higher level opcodes,
such as ADDC, OR, and JUMP. While these opcodes are actually implemented as MOVE instructions between certain
register locations, the encoding is handled by the assembler and need not be a concern to the programmer. The unused
"empty" locations in the System Register Modules are used for these higher level opcodes.
The instruction set is designed to be highly orthogonal. All arithmetic and logical operations that use two registers can use
any register along with the accumulator. Data can be transferred between any two registers in a single instruction.
2.2 – Register Space
The DS4830A provides a total of 13 register modules broken up into two different groups. These groupings are
descriptive only, as there is no difference between accessing the two register groups from a programming perspective.
The two groups are:
1. System Registers: These are modules 8h, 9h, and Bh through Fh. The System Registers in the DS4830A are
used to implement higher level opcodes as well as the following common system features.
• 16-bit ALU and associated status flags (zero, equals, carry, sign, overflow)
• 16 working accumulator registers, each 16-bit, along with associated control registers
• Instruction pointer
• Registers for interrupt control, handling, and identification
• Auto-decrementing Loop Counters for fast, compact looping
• Two Data Pointer registers and a Frame Pointer for data memory access
2. Peripheral Registers: These are the lower six modules (Modules 0h through 5h). The Peripheral Registers in the
DS4830A are used for functionalities such as ADC, Fast Comparator, DAC, PWM Outputs, Timers, Sample and
Hold, 3-Wire, I
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C Master and Slave, SPI Master and Slave, 31-GPIO pins, etc. The Peripheral Registers are not
used to implement opcodes.
Each System Register module has 16 registers, while each Peripheral Register module has 32 registers. The number of
cycles required to access a particular register depends upon the register’s index within the module. The access times
based upon the register index are grouped as follows:
• The first eight registers (index 0h to 7h) in each module may be read from or written to in a single cycle
• The second eight registers (index 8h to 0Fh) may be read from in a single cycle and written to in two cycles (by
using the prefix register PFX).
• The last sixteen registers (10h to 1Fh) in Peripheral Register modules may be read or written in two cycles
(always requiring use of the prefix register PFX).
Registers may be 8 or 16 bits in length. Some registers may contain reserved bits. The user should not write to any
reserved bits. Data transfers between registers of different sizes are handled as shown in Table 2-1.
• If the source and destination registers are both 8 bits wide, data is copied bit to bit.
• If the source register is 8 bits wide and the destination register is 16 bits wide, the data from the source register is
transferred into the lower 8 bits of the destination register. The upper 8 bits of the destination register are set to
the current value of the prefix register; this value is normally zero, but it can be set to a different value by the
previous instruction if needed. The prefix register reverts back to zero after one cycle, so this must be done by the
instruction immediately before the one that will be using the value.
• If the source register is 16 bits wide and the destination register is 8 bits wide, the lower 8 bits of the source are
transferred to the destination register.
• If both registers are 16 bits wide, data is copied bit to bit.
The above rules apply to all data movements between defined registers. Data transfer to/from undefined register locations
has the following behavior:
• If the destination is an undefined register, the MOVE is a dummy operation but may trigger an underlying
operation according to the source register (e.g., @DPn--).
• If the destination is a defined register and the source is undefined, the source data for the transfer will depend
upon the source module width. If the source is from a module containing 8-bit or 8-bit and 16-bit source registers,