Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 98)

DS4830A User’s Guide
98
Detect I 2 C Start
I2CSRI = 1
I2CBUS = 1
I2CBUSY = 1
Receive
Addr[6:0] + /R\W
Matched
Enabled Slave
Addresses
Transmit
I2CACK
Set I2CMODE bit
according to /R\W
I2CAMI = 1 and set
CUR_SLA according
to Matched Slave
address
I2CBUSY = 0
No
Yes
Receiving Slave
Address
Transmitting
Data
Update Transmit
Pages at the I 2 C
Start Interrupt
Is Active
Transmit Page
Generated
Threshold
Interrupt
Transmit Shift
Register Byte, MSB
First
8 Bits
Transmit
?
Receive Acknowledge and
set I2CNACKI accordingly
Yes
I2CTXI = 1
I2CBUSY = 0
No
Update Transmit
page with new
transmit data
Receiving Data
Detect 1 st SCL Rising
Edge
I2CBUSY = 1
Receive a Bit into
Shift Register MSB
first
8 Bits
Received
?
No
RX FIFO
FULL
?
Set FULL bit
and set
I2CACK = 1
Yes
No
Yes
Load Shift Register
into RX FIFO
Send I2CACK
I2CBUSY = 0
Figure 11-4: Slave I
2
C Data Flow Using 8-Byte Transmit Page and 8-Byte Receive FIFO
11.1.7 – Transmitting Data
The DS4830A I
2
C Slave Controller enters into data transmission mode after receiving a matching slave address with
the R/
W bit set to 1.
11.1.7.1 – Normal Mode Data Transmission
The steps of data transmission are shown in Figure 11-2. Data transmission is started by software loading data into
the I2CBUF_S register. Loading I2CBUF_S causes the I2CBUSY bit in I2CST_S to be set. Once I2CBUSY bit is set,
a write to I2CBUF_S is ignored. The first bit of data (most significant bit) is shifted to SDA when SCL is low. Each of
the next seven bits is then shifted following high to low transitions of SCL.
Following the 8
th
bit data (least significant bit) being shifted to SDA, the SDA line is released by the slave controller.
This allows the host to signal an ACK or NACK during the 9
th
clock cycle. The I
2
C slave controller samples the
acknowledge bit following the 9
th
SCL rising edge. After the acknowledge bit is sampled, the I
2
C slave controller
performs the following tasks: