Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 157)

DS4830A User’s Guide
157
Table 19-1: Watchdog Operating States
EWT EWDI WDIF ACTIONS
x X 0 No interrupt has occurred.
0 0 x Watchdog disable, clock is gated off.
0 1 1 Watchdog interrupt has occurred.
1 0 1
No interrupt has been generated. Watchdog reset will occur in 512 system
clock cycles if RWT is not set or WDIF not cleared.
1 1 1
Watchdog interrupt has occurred. Watchdog reset will occur in 512 system
clock cycles if RWT is not set or WDIF not cleared.
19.2.1 – Watchdog Timer Interrupt Operation
The watchdog interrupt is enabled using the Enable Watchdog Timer Interrupt (WDCN.EWDI) bit. When the timeout
occurs, the watchdog timer will set the Watchdog Interrupt Flag bit (WDCN.WDIF), and an interrupt will occur if the
interrupt global enable (IC.IGE) and system interrupt mask (IMR.IMS) are set and an interrupt is not currently being
serviced (IC.INS = 0). The Watchdog Interrupt Flag must be cleared by software.
19.2.2 – Watchdog Timer Reset Operation
In order to reset the DS4830A, the watchdog timer reset function must be enabled by setting the Enable Watchdog
Timer Reset (WDCN.EWT) bit. When a watchdog timeout occurs, the WDIF flag will be set and an interrupt will be
generated if enabled. Following the timeout, the watchdog will count an additional 512 system clock cycles. To
avoid a reset, software must either set the RWT bit or clear the EWT bit. This can occur at any time during the
watchdog timer interval or the additional 512 system clock cycles after WDIF is set. At the end of the 512 system
clock cycles the DS4830A will be reset. When the reset occurs, the Watchdog Timer Reset Flag (WDCN.WTRF) will
automatically be set to indicate the cause of the reset. Software must clear this bit manually.
19.2.3 – Watchdog Timer Applications
Using the watchdog interrupt during software development can allow the user to select ideal watchdog reset
locations. Code is first developed without enabling the watchdog interrupt or reset functions. Once the program is
complete, the watchdog interrupt function is enabled to identify the required locations in code to set the RWT bit.
Incrementally adding instructions to reset the watchdog timer prior to each address location (identified by the
watchdog interrupt) will allow the code to eventually run without receiving a watchdog interrupt. At this point the
watchdog timer reset can be enabled without the potential of generating unwanted resets. At the same time the
watchdog interrupt may also be disabled. Proper use of the watchdog interrupt with the watchdog reset allows
interrupt software to survey the system for errant conditions.
When using the watchdog timer as a system monitor, the watchdog reset function should be used. If the interrupt
function were used, the purpose of the watchdog would be defeated. For example, assume the system is executing
errant code prior to the watchdog interrupt. The interrupt would temporarily force the system back into control by
vectoring the CPU to the interrupt service routine. Restarting the watchdog and exiting by an RETI or RET, would
return the processor to the errant code. By using the watchdog reset function, the processor is restarted from the
beginning of the program, and therefore placed into a known state.
The watchdog timer is controlled by the Watchdog Timer Control Register, WDCN. The WDCN register is one of the
system register and is located in Module 8, Register 19. The bit names and description of WDCN are listed in Table
19-2.