Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 85)

DS4830A User’s Guide
85
10.1.6 – Generating a STOP
To end an I
2
C transfer, a STOP must be transmitted. A STOP is generated by setting the I2CSTOP bit. The
master I
2
C controller’s flow when attempting to issue a STOP command is shown in Figure 10-3.
If the I2CSTOP bit is set when the I
2 C Controller is in the middle of a byte transfer (after the first bit rising edge), it will
wait for the current byte transfer to finish (after the 9 th bit) before generating the STOP condition.
Because the SDA line is feedback into the device, when the master generates a STOP, it will also detect the
STOP condition. When a STOP condition is detected, the I
2
C STOP interrupt flag (I2CSPI) will be set and an
interrupt will be generated enabled. The I2CBUS bit will be cleared to indicate that the I
2
C bus is now idle and the
I2CSTOP bit will be cleared.
When the master I
2
C controller attempts to generate the STOP condition, it will also start the timeout timer if this
feature is enabled. If a timeout is generated before the STOP condition is detected, a timeout will occur. When a
timeout occurs, the I2CTOI bit will be set, which can generate an interrupt if enabled, and the I2CSTOP bit will also
be cleared to 0.
10.1.7 – Transmitting a Slave Address
The first byte after an I
2 C START or restart condition is the slave address byte. This byte, which is transmitted by the
master, contains seven bits of slave address followed by the R/
W bit. The transmission of the slave address begins
with writing 7-bit slave address + the R/
W bit to I2CBUF_M.
Figure 10-4 shows the format for slave address 36h in write mode. The address bits A[6:0], which is the slave
address the R/
W bit is written to I2CBUF_M[6:0]. Bit 0 of I2CBUF_M is copied to bit 0 I2CMODE of the I2CSLA_M
register. When bit 0 is ‘1’, the I
2
C master is operating in receiver mode (data read from slave). When bit 0 is ‘0’, the
I
2
C master is operating in transmitter mode (data write to slave).
Figure 10-4: Slave Address Format
After the slave address has been written to I2CBUF_M, the I
2 C master controller will set the I2CBUSY bit to indicate
the controller is actively participating in a transaction. The eight bits in I2CBUF_M[7:0] will be transmitted on SDA.
The data for the 8
th
bit transmit, which is the R/
W bit, is copied in the I2CMODE bit of the I2CSLA_M register. The
I
2
C master then issues the 9
th
clock, which is for the acknowledge bit, and reads SDA for an acknowledgment from a
slave device. The I
2
C master controller then performs the following steps. This is illustrated in Figure 10-5.
• Set the I2CNACKI bit with the value of the received acknowledgement.
• The I2CTXI bit will then be set to indicate a byte was transmit.
• Clear the I2CBUSY flag.
Upon transmitting the slave data byte (7 bits of slave address + R/
W bit + acknowledge), the I 2
C master controller
will enter one of the three states.
• Data Transmit: The I2CMODE (R/ W) bit was set to a 0, indicating that the master will be writing data to a
slave device. The DS4830A will retain control of the SDA line.
• Data Receive: The I2CMODE (R/ W) bit was set to a 1, indicating that the master will be receiving data from
a slave. The DS4830A releases control of SDA to allow a slave device to output data. The DS4830A
Master I
2
C controller automatically begins clocking bytes of data from the slave.
• The slave address was NACKed. The master I 2
C controller will retain control of SDA and is able to transmit
data.
10.1.8 – Transmitting Data
The DS4830A I
2
C Master Controller enters into data transmission mode after transmitting a slave address with the
R/
W bit (I2CMODE) set to a 0. The steps of data transmission are shown in Figure 10-5. Data transmission is
started by software loading a byte of data into the I2CBUF_M register. Loading I2CBUF_M causes the I2CBUSY bit