Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 59)

DS4830A User’s Guide
59
7.2.6.1 – ADC Configuration Register (ADDATA when ADCFG = 1 and ADCAVG = 0)
When ADCFG = 1 and ADCAVG = 0, writing to the ADDATA register writes to one of the configuration registers.
The configuration register written to is selected by the ADIDX[4:0] bits. The ADIDX[4:0] bits are automatically
incremented after a write to ADDATA. This allows consecutive writes of ADDATA to setup consecutive configuration
registers. The configuration registers are reset to ‘0’ on all forms of reset.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name - ADGAIN[1:0] ALT_LOC[4:0] ADACQEN ADALIGN ADDIFF ADCH[4:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r rw* rw* rw* rw* rw* rw* rw* rw* rw* rw* rw* rw* rw* rw* rw*
* When ADCFG = 1, unrestricted read, but can only be written to when ADCONV = 0.
BIT
NAME DESCRIPTION
15 - Reserved. The user should not write to this bit.
14:13 ADGAIN[1:0] ADC Gain Select. This bit selects the ADC scale factor.
ADGAIN[1:0] ADC SCALE Full Scale (typ)
00 ADCG1 1.2V
01 ADCG2 0.6V
10 ADCG3 2.4V
11 ADCG4 6.55*
* When the ADCG4 select, the ADC input should not be above 3.6V. It is limited by V
DD
operating range.
12:8 ALT_LOC[4:0] Alternate location for conversion result. These bits specify the alternate location for
storing the ADC conversion result when LOC_OVR bit in the ADCN register is set to ‘1’.
7 ADACQEN ADC Acquisition Extension Enable. Setting this bit to ‘1’ enables additional acquisition
time to be inserted prior to this conversion. Clearing this bit to ‘0’ disables the extended
acquisition time.
6 ADALIGN ADC Data Alignment Select. This bit selects the ADC data alignment mode. Setting this
bit to ‘1’ returns ADC data left aligned in ADDATA [15:2] with ADDATA[1:0] zero padded.
Clearing this bit to ‘0’ returns ADC data in right aligned format in ADDATA[13:0] with
ADDATA[15:14] sign-extended by ADDATA[13].
5 ADDIFF ADC Differential Mode Select. This bit selects the ADC conversion mode. When this bit
is set to ‘1’, the ADC conversion is in differential mode. When this bit is cleared to ‘0’, the
ADC conversion is performed in single-ended mode. In single-ended mode, the sample is
measured between the ADC Channel and ground.
4:0 ADCH[4:0] ADC Channel Select. These bits select the input channel source for configuration of ADC
conversion.
ADCH [4:0] ADDIFF = 0 ADDIFF=1
00000 ADC-S0 ADC-D0P- ADC-D0N
00001 ADC-S1 ADC-D1P- ADC-D1N
00010 ADC-S2 ADC-D2P- ADC-D2N
00011 ADC-S3 ADC-D3P- ADC-D3N
00100 ADC-S4 ADC-D4P- ADC-D4N
00101 ADC-S5 ADC-D5P- ADC-D5N
00110 ADC-S6 ADC-D6P- ADC-D6N
00111 ADC-S7 ADC-D7P- ADC-D7N
01000 ADC-S8 NOT VALID
01001 ADC-S9 NOT VALID
01010 ADC-S10 NOT VALID
01011 ADC-S11 NOT VALID
01100 ADC-S12 NOT VALID
01101 ADC-S13 NOT VALID
01110 ADC-S14 NOT VALID
01111 ADC-S15 NOT VALID
10000 ADC-REFINA ADC-REFINA
10001 ADC-REFINB ADC-REFINB
10010 VDD VDD
10011 DAC_INT_REF DAC_INT_REF
10100- 11000 NOT VALID NOT VALID
11001 ADC OFFSET ADC OFFSET