Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 88)

DS4830A User’s Guide
88
10.1.10 – I
2
C Master Clock Stretching
The Master I
2
C Controller is capable of clock stretching at the end of each transfer cycle. Clock stretching is when
SCL is held low. If the I 2 C Clock Stretch Enable bit (I2CSTREN) is set to a 1, the I 2 C controller will hold SCL low
after the clock pulse defined by the I
2
C Clock Stretch Select bit (I2CSTRS). If I2CSTRS=0, the I
2
C controller will hold
SCL low after the falling edge of the 9 th clock pulse. If I2CSTRS=1, the I 2 C controller will hold SCL low after the
falling edge of the 8
th
clock pulse. When the I
2
C controller is holding SCL low, the I
2
C Clock Stretch Interrupt flag
(I2CSTRI) will be set, which can generate an interrupt if enabled. The I
2
C slave controller will hold SCL low until
I2CSTRI is cleared to 0 by software.
If clock stretching is enabled after the 8
th
clock pulse, the master I
2
C controller will continue outputting the value of
the I2CACK bit until clock stretching is released by clearing I2CSTRI. This allows software time to examine the data
that was received prior to sending an ACK or NACK to the slave. The continuous output of I2CACK will occur even if
the master I
2 C controller is transmitting data. In this mode, the slave should be sending the acknowledgement. To
allow the slave to send the proper acknowledgement, the I2CACK bit should be set to a 1, which prompts the master
I
2
C controller to release SDA.
The Master I
2
C Controller may need to use clock stretching when receiving data from a slave. When receiving data,
the master I
2
C controller automatically generates clock pulses. Without using clock stretching, this automatic clock
generation is only halted when a STOP command is issued or a receive overrun occurs. If clock stretching is
enabled, software can control when each byte of data is clocked from the slave device.
10.1.11 – Resetting the I
2
C Master Controller
The I
2
C master controller can be reset by disabling the I
2
C master controller by writing ‘0’ at I2CEN = 0 in the I2CCN
I2CCN_M register. A reset will force the master I
2
C controller to release both MSDA and MSCL if they are being held
low by the I 2 C master controller. A reset may reset few or all bits of I2CCN, I2CST and I2CBUF I 2 C registers, and
reset the I
2
C master controller’s internal state machine. Following a reset, the I
2
C master controller must be re-
initialized before it can be used again.
After a reset, the master I
2
C controller will be in a known state but the slave devices may be in an unknown state. It
is recommended that the master I
2
C controller attempts to reset the slave devices prior to beginning communication.
A reset of slave devices can be performed by outputting at least 9 clock pulses on the MSCL line while MSDA is
high. This easiest way to achieve this is to use MSDA and MSCL as GPIO pins (see the GPIO section) while the
master I
2
C controller is disabled (I2CEN=0). After the 9 clock pulses, a STOP command should be generated. This
can be done either using GPIO, or by enabling the master I
2
C controller and generating a STOP.