Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 74)

DS4830A User’s Guide
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By default, the external channels GP0-15 are general-purpose input. The DS4830A has the Pin Select Register
(PINSEL). The PINSEL register is used to configure the external channels as an analog pin for ADC or/and Quick
Trip use. Each bit location in this register corresponds to the ADC/Quick Trip input pin.
Table 9-1: Low and High Thresholds Configuration and List Creation
RW_LST LTHT QTIDX REGISTER SELECTED
0 0 N(0 to 15) Low threshold configuration for the channel defined in list N
0 1 N(0 to 15) High threshold configuration for the channel defined in list N
1 X N(0 to 15) N
th
register of list configuration
Thresholds Configuration
Each configuration has two threshold registers to configure low and high threshold. Each threshold register is
addressed by the QTIDX[3:0] bits. These bits are auto incremented on any read or write operation to the QTDATA
register. The low trip thresholds are configured by writing to the QTDATA register when the RW_LST and LTHT bits
are set to ‘0’. The high trip thresholds are configured by writing to the QTDATA register when the RW_LST bit is set
to ‘0’ and LTHT bit is set to ‘1’.
List Creation
As shown in Figure 9-1, the quick trip controller has 16 list registers. These are configured by writing to the QTDATA
register when the RW_LST bit is set to ‘1’. The list address is addressed by the QTIDX[3:0] bits. Each list register
uses only lower 5 bits. The first 4 lower bits CHSEL [3:0] specifies the quick trip input channel. The DIFF bit selects
between single-ended mode (when DIFF bit is set to ‘0’) and differential mode (when DIFF bit is set to ‘1’) quick trip
comparison. The start and stop addresses of the list are provided by the Quick Trip List Register (QTLST). Any
channel can be used multiple times at any location in the list.
See Section 9.2 - Quick Trip Register Descriptions for details.
As shown in Figure 9-1, the quick trip sequencer selects a channel from 16 external channels. The quick trip
controller has an internal 10-bit DAC which generates voltage for low and high threshold comparisons with the
external channel input. The quick trip is also called a “Fast Comparator” as it compares the input with threshold using
the fast comparator. The conversion time is 1.6µs for each threshold; so each channel’s thresholds are compared in
3.2µs (1.6µs for low trip threshold + 1.6µs for high trip threshold).
9.1.1 – Quick Trip List Sequencing
The DS4830A quick trip controller performs the user defined sequence of up to 16 single-ended or 8 differential
external channels conversions.
A sequence is setup in the QTLST register by defining the starting conversion configuration address (QTSTART) and
an ending conversion configuration address (QTEND). The configuration start address designates the configuration
register to be used for the first conversion in a sequence. The configuration end address designates the
configuration register used for the last conversion in a sequence. A single channel conversion can be viewed as a
special case for sequence conversion, where the starting and ending configuration address is the same. The
configuration registers can be viewed as a circular register array where QTSTART does not have to be less than
QTEND. For example, if QTSTART = 1 and QTEND = 5, then the sequence of conversions would be configurations
1, 2, 3, 4, 5. If QTSTART = 5 and QTEND = 1, then the sequence of conversions would be configurations 5, 6, 7 . . .
15, 0, 1.
9.1.2 – Operation
The quick trip is enabled by setting the Quick Trip Enable (QTEN) bit to ‘1’ in the QTCN register. The Quick Trip
Controller takes ~120 core clocks to wake up after enable and then starts scanning through the list of channels
specified in the channel list register QTLST continuously in the round robin sequence. The quick trip sequence reads
the list, selects the input channel and reads the low trip threshold and performs 10-bit comparison, then reads the
high trip threshold and again performs 10-bit comparison. The quick trip has separate interrupt flag registers for the
low and high trip threshold. The low trip interrupt flag is set when the input voltage is less than the configured low
threshold. Similarly, the high trip interrupt flag is set when the input voltage is greater than the configured high
threshold. The interrupt can be generated if enabled.
The channel list can be filled up using the QTDATA register by setting the RW_LST bit to ‘1’ in the QTCN register.
For example to scan channels S5, S6 and S14-15 having configurations for channels 5 & 6 in the single-ended
mode, channel 7 (S14-S15) in the differential mode and channel 6 again (any channel can be configured multiple