Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 213)

DS4830A User’s Guide
213
MOVE dst, src
(continued)
Destinati
on
Specifier
Codes
dst
dst Bit
Encoding
ddd dddd
16 or 8
Bits
Description
NUL 111 0110
8/16
Null (virtual) destination. Intended as a bit bucket to assist software with pointer
increments/decrements.
MN[n] nnn 0NNN
8/16
nnnn selects one of first 8 registers in module NNN; where NNN= 0-5. Access to next 24 using
PFX[n].
AP 000 1000 8 Accumulator Pointer
APC 001 1000 8 Accumulator Pointer Control
PSF 100 1000 8 Processor Status Flag Register
IC 101 1000 8 Interrupt and Control Register
IMR 110 1000 8 Interrupt Mask Register
A[n] nnn 1001 16 nnn selects 1 of first 8 accumulators: A[0]..A[7]
Acc 000 1010 16 Active Accumulator = A[AP].
PFX[n] nnn 1011 8 nnn selects one of 8 Prefix Registers
@++SP 000 1101 16 16-bit word @SP, pre-increment SP
SP 001 1101 16 Stack Pointer
IV 010 1101 16 Interrupt Vector
LC[n] 11n 1101 16 n selects one of 2 loop counter registers
@BP[Offs] 000 1110 8/16 Data memory @BP[Offs]
@BP[++Offs] 001 1110 8/16 Data memory @BP[Offs]; pre increment OFFS
@BP[--Offs] 010 1110 8/16 Data memory @BP[Offs]; pre decrement OFFS
OFFS 011 1110 8 Frame Pointer Offset from Base Pointer (BP)
DPC 100 1110 16 Data Pointer Control Register
GR 101 1110 16 General Register
GRL 110 1110 8 Low byte of GR register
BP 111 1110 16 Frame Pointer Base Pointer (BP)
@DP[n] n00 1111 8/16 Data memory @DP[n]
@++DP[n] n01 1111 8/16 Data memory @DP[n], pre increment DP[n]
@--DP[n] n10 1111 8/16 Data memory @DP[n], pre decrement DP[n]
DP[n] n11 1111 16 n selects one of 2 data pointers
2-Cycle Destination Access Using PFX[n] register (see Special Notes)
SC
000 1000 8 System Control Register
CKCN 110 1000 8 Clock Control Register
WDCN 111 1000 8 Watchdog Control Register
A[n] nnn 1001 16 nnn selects 1 of second 8 accumulators A[8]..A[15]
GRH 001 1110 8 High byte of GR register
Data Transfer Rules
dst (16-bit)  src (16-bit): dst[15:0]  src[15:0]
dst (8-bit)  src (8-bit): dst[7:0]  src[7:0]
dst (16-bit)  src (8-bit): dst[15:8]  00h *
dst[7:0]  src[7:0]
dst (8-bit)  src (16-bit): dst[7:0]  src[7:0]
* Note: The PFX[0] register may be used to supply a separate high order data byte for this type of transfer.