Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 180)

DS4830A User’s Guide
180
22.1.1 – Password Protection
The DS4830A uses a password to protect the contents of the program memory from simple access and viewing.
The password resides in the 32 bytes of program memory at byte address 0020h through 003Fh. A valid password
is defined as any value that does not contain all 0000h or FFFFh. Following a reset, the Password Lock Bit (PWL) in
the SC register will be set if the DS4830A contains a valid password.
To protect the program memory, DS4830A grants full access to in-system programming, in-application programming
or in-circuit debugging only after a password match has occurred. When a password match occurs, the PWL bit will
be cleared to 0. When bootloading the device, the password can be matched using the Password Match command,
through either the JTAG or I
2
C interface.
22.1.2 – Entering JTAG Bootloader
To enable the Bootstrap loader and establish a desired communication channel via JTAG, the System Programming
instruction (100b) must be loaded into the TAP instruction register using the IR-Scan sequence. The TAP retains the
System Programming instruction until a new instruction is shifted in or the TAP controller returns to the Test-Logic-
Reset state. See Section 16 –Test Access Port for more information regarding the JTAG port.
Once the instruction is latched in the instruction parallel buffer (IR[2:0]) and is recognized by the TAP controller in the
Update-IR state, a 3-bit data shift register is activated as the communication channel for DR-Scan sequences. This
3-bit shift register formed between the TDI and TDO pins is directly interfaced to the 3-bit Serial Programming Buffer
(SPB). Table 22-1 provides a detailed description of the System Programming Buffer (SPB). The data content of
the SPB is reflected in the ICDF register, which allows read and write access by the CPU. These bits are cleared by
power-on reset or Test-Logic-Reset of the TAP controller.
Table 22-1: System Programming Buffer (SPB)
BIT NAME DESCRIPTION
2:1 PSS[1:0]
Programming Source Select (PSS1:PSS0). These bits select the programming interface
source.
PSS1 PSS0 Programming Source
0 0 JTAG
0 1 I
2
C
1 x Exit loader
0 SPE
System Programming Enable (SPE). Setting this bit to a logic 1 denotes that JTAG
bootloading is desired upon exiting reset. The logic state of SPE is examined by the Utility
ROM following a reset to determine the program flow. When SPE=1, the Bootstrap
Loader selected by the PSS[1:0] bits will be activated to perform a Bootstrap Loader
function. If SPE=0, the Utility ROM will determine if I
2
C Bootloading is required before
transferring execution control to the normal user program.
Following a reset, if the System Programming Buffer is set for JTAG bootloading, the bootload routine will be
entered. The host must now load the Debug instruction (010b) into the TAP instruction register (IR[2:0]), which
enables the 10-bit Debug shift register between TDI and TDO. When operating in JTAG bootloader mode, the
debug state machines are disabled and the sole purpose of the debug hardware is to simultaneously transfer the
data byte shifted in from the host to the In-Circuit Debug Buffer Register (ICDB) and transfer the contents of an
internal holding register (loaded by ROM code writes of ICDB) into the shift register for output to the host. The 8
most significant bits of the 10-bit shift register interface directly to the ICDB. The transfer between the shift register
and the ICDB register occurs on the falling edge of TCK at the Update-DR state. The debug hardware additionally
clears the TXC bit in the ICDF register at this point. The ROM loader code controls the status bit output to the host
by asserting TXC=1 when it has valid data to be shifted out.
The 2 least significant bits of the 10-bit shift register are status bits. The JTAG bootloader has the benefit of using
the same status bit handshaking hardware that is used for in-circuit debugging. The description of the status bits is
described in Table 22-2.
Note: When using the JTAG port, the clock rate (TCK) must be kept below 1/8 of the system clock rate.