Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 97)

DS4830A User’s Guide
97
11.1.6 – Advanced Mode Operation RX FIFO and TX Pages
The DS4830A I
2
C slave controller has a few features that make 400kHz I
2
C communication without clock stretching
possible.
Shift Register
Address Match
I2CSLA4_S
I2CSLA3_S
I2CSLA2_S
I2CSLA_S
8-Byte
Receive FIFO
MUX
TX0 4 WORDS PAGE
TX2 4 WORDS PAGE
TX3 4 WORDS PAGE
TX4 4 WORDS PAGE
SLA[3:0]
SDA
SCL
SLA[3:0]
Write through
I2CBUF_S
Read through
I2CBUF_S
Figure 11-3: I
2
C Slave Block Diagram with RX FIFO and TX Pages
The I
2
C controller allows the user to define a memory map structure in the user SRAM for each individual slave
address. This is done using the MEM_ADDR[7:0] and PAGE[2:0] bits in the MADDR, MADDR2, MADDR3, and
MADDR4 registers. These register bits 10:0 are used to define start address (SRAM Address) of the memory map
structure and bit 12 is used to define memory rollover boundary between 128 and 256. The I
2
C controller maintains
the memory address of the individual slave address in the read memory address pointer RPNTR register. Each slave
address has dedicated RPNTR, which is selected based on the SLA[3:0] bits. The read address (maintained by
RPNTR) is automatically incremented by 1 word after every write to the I2CBUF_S. The I
2
C controller handles 128 or
256 boundary rollover internally on the read memory address.
11.1.6.1 – RX FIFO
The DS4830A I
2
C controller has an 8-byte receive FIFO. This FIFO is shared among the enabled slave addresses.
The receive FIFO is controlled using the I2CRXFIE (I 2 C Receive FIFO Interrupt Enable) and I2CRXST (I 2 C Receive
FIFO Status Flags) registers and is read from the I2CBUF_S register. See the individual bit description in I 2 C Slave
Controller Register Description section. This FIFO is shown in Figure 11-3.
11.1.6.2 – Transmit Pages
The I
2
C controller has four Transmit (TX) pages, each dedicated to a specific slave address. Each of the TX pages
holds 4 16-bit words. When transmitting data, the controller automatically selects one of the TX pages based upon
the SLA[3:0] bits in the CUR_SLA (Current Slave Address) which is set during a successful slave address match
event. The TX Pages are filled by first setting the SLA[3:0] bits, then writing data to the I2CBUF_S register. I
2
C
transmission using the TX Pages is controlled using the I2CTXFIE (I
2
C Transmit Interrupt Enable) and I2XTXFST
(I
2
C Transmit Page Status Flags) registers. See the individual bit description in I
2
C Slave Controller Register
Description section. The TX pages are shown in Figure 11-3.
11.1.6.3 Advanced Mode Memory Address Detection
The I
2 C Slave Controller provides an option to automaticcaly detect the memory address being accessed by the
host. The MADDR_EN bits in the CUR_SLA register enable the memory address to be automatically captured by the
I
2
C controller. Following an address match with I2CMODE = 0 (Write), the I
2
C slave controller knows that the next
byte of data to be received is the memory address of the memory map and copies the received byte into the
MEM_ADDR[7:0] bits in the MPNTR (Memory address pointer) register with PAGE[2:0] from active slave address.
When the memory address is captured, the MADI bit in the I2CST2_S register will be set, which can generate an
interrupt if enabled. The MPNTR shows the current memory address of the active slave address. To enable memory
address dection, the proper MADDR_EN bit must be set and the RX FIFO must be enabled.