Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 161)

DS4830A User’s Guide
161
20.2 – TAP State Control
The TAP provides an independent serial channel to communicate synchronously with the host system. The TAP
state control is achieved through host manipulation of the Test Mode Select (TMS) and Test Clock (TCK) signals.
The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement
between the TAP states. The TDI input and TDO output are meaningful once the TAP is in a serial shift state (i.e.
Shift-IR or Shift-DR).
20.2.1 – Test-Logic-Reset
On a power-on reset, the TAP controller is initialized to the Test-Logic-Reset state and the instruction register (IR2:0)
is initialized to the By-Pass instruction so that it will not affect normal system operation. No matter what the state of
the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. The
controller remains in the Test-Logic-Reset state if TMS remains high. An erroneous low signal on the TMS may
cause the controller to move into the Run-Test-Idle state but no disturbance is caused to system operation if the
TMS signal is returned and kept at the intended logic high for three rising edges of TCK since this returns the
controller to the Test-Logic-Reset state.
20.2.2 – Run-Test-Idle
As illustrated in Figure 20-2, the Run-Test-Idle state is simply an intermediate state for getting to one of the two state
sequences in which the controller performs meaningful operations:
• Controller state sequence (IR-Scan), or
• Data register state sequence (DR-Scan)
20.2.3 – IR-Scan Sequence
The controller state sequence allows instructions (e.g. ‘Debug’ and ‘System Programming’) to be shifted into the
instruction register starting from the Select-IR-Scan state. In the TAP, the instruction register is connected between
the TDI input and the TDO output. Inside the IR-Scan Sequence, the Capture-IR state loads a fixed binary pattern
(001b) into the 3-bit shift register and the Shift-IR state causes shifting of TDI data into the shift register and serial
output to TDO, least significant bit first. Once the desired instruction is in the shift register, the instruction can be
latched into the parallel instruction register (IR2:0) on the falling edge of TCK in the Update-IR state. The contents of
the 3-bit instruction shift register and parallel instruction register (IR2:0) are summarized with respect to the TAP
controller states in Table 20-2.
Table 20-2: Instruction Register Content vs. TAP Controller State
TAP
CONTROLLER STATE
INSTRUCTION SHIFT REGISTER
PARALLEL (3-BIT)
INSTRUCTION REGISTER (IR2:0)
Test-Logic-Reset Undefined Set to By-pass (011b) Instruction
Capture-IR Load 001b at the rising edge of TCK Retain last state
Shift-IR
Input data via TDI and Shift towards
TDO at the rising edge of TCK
Retain last state
Exit1-IR
Exit2-IR
Pause-IR
Retain last state Retain last state
Update-IR Retain last state Load from shift register at the falling edge of TCK
All other states Undefined Retain last state
When the parallel instruction register (IR2:0) is updated, the TAP controller decodes the instruction and performs any
necessary operations, including activation of the data shift register to be used for the particular instruction during
data register shift sequences (DR-Scan). The length of the activated shift register depends upon the value loaded to
the instruction register (IR2:0). The supported instruction register encodings and associated data register selections
are shown in Table 20-3.