DS4830A User’s Guide
2
Contents
SECTION 1 – OVERVIEW .................................................................................................................................................... 11
SECTION 2 – ARCHITECTURE ........................................................................................................................................... 13
2.1 – Instruction Decoding ................................................................................................................................................. 13
2.2 – Register Space ......................................................................................................................................................... 14
2.3 – Memory Types .......................................................................................................................................................... 15
2.3.1 – Flash Memory .................................................................................................................................................... 15
2.3.2 – SRAM Memory ................................................................................................................................................... 15
2.3.3 – Utility ROM ......................................................................................................................................................... 15
2.3.4 – Stack Memory .................................................................................................................................................... 16
2.4 – Program and Data Memory Mapping and Access ................................................................................................... 16
2.4.1 – Program Memory Access .................................................................................................................................. 16
2.4.2 – Program Memory Mapping ................................................................................................................................ 17
2.4.3 – Data Memory Access ......................................................................................................................................... 17
2.4.4 – Data Memory Mapping....................................................................................................................................... 18
2.5 – Data Alignment ......................................................................................................................................................... 22
2.6 – Reset Conditions ...................................................................................................................................................... 22
2.6.1 – Power-On/Brownout Reset ................................................................................................................................ 22
2.6.2 – Watchdog Timer Reset ...................................................................................................................................... 23
2.6.3 – External Reset ................................................................................................................................................... 23
2.6.4 – Internal System Resets ...................................................................................................................................... 24
2.6.5 – Software Reset .................................................................................................................................................. 24
2.7 – Clock Generation ...................................................................................................................................................... 24
SECTION 3 – SYSTEM REGISTER DESCRIPTIONS ......................................................................................................... 25
3.1 – Accumulator Pointer Register (AP, 08h[00h]) .......................................................................................................... 27
3.2 – Accumulator Pointer Control Register (APC, 08h[01h]) ........................................................................................... 27
3.3 – Processor Status Flags Register (PSF, 08h[04h]) ................................................................................................... 27
3.4 – Interrupt and Control Register (IC, 08h[05h]) ........................................................................................................... 28
3.5 – Interrupt Mask Register (IMR, 08h[06h]) .................................................................................................................. 28
3.6 – System Control Register (SC, 08h[08h]) .................................................................................................................. 28
3.7 – Interrupt Identification Register (IIR, 08h[0Bh]) ........................................................................................................ 29
3.8 – Watchdog Control Register (WDCN, 08h[0Fh]) ....................................................................................................... 29
3.9 – Accumulator n Register (A[n], 09h[nh]) .................................................................................................................... 29
3.10 – Prefix Register (PFX[n], 0Bh[n] .............................................................................................................................. 29
3.11 – Instruction Pointer Register (IP, 0Ch[00h]) ............................................................................................................ 30
3.12 – Stack Pointer Register (SP, 0Dh[01h]) ................................................................................................................... 30
3.13 – Interrupt Vector Register (IV, 0Dh[02h]) ................................................................................................................. 30
3.14 – Loop Counter 0 Register (LC[0], 0Dh[06h]) ........................................................................................................... 30
3.15 – Loop Counter 1 Register (LC[1], 0Dh[07h]) ........................................................................................................... 30
3.16 – Frame Pointer Offset Register (OFFS, 0Eh[03h]) .................................................................................................. 30
3.17 – Data Pointer Control Register (DPC, 0Eh[04h]) ..................................................................................................... 31