Altera CPRI IP Core User Manual

Page 10

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1–4

Chapter 1: About This MegaCore Function

CPRI IP Core Features

CPRI MegaCore Function

December 2013

Altera Corporation

User Guide

Supports the following additional CPRI link features:

Programmable CPRI communication line rate (to 614.4, 1228.8, 2457.6, 3072.0,
4915.2, 6144.0, or 9830.4 Mbps) using Altera on-chip high-speed transceivers.

Programmable operation mode: CPRI link master or CPRI link slave.

Auto-rate negotiation support.

Scrambling and descrambling at 4915.2 Mbps, 6144.0 Mbps, and 9830.4 Mbps.

Receiver (Rx) delay measurement.

Transmitter (Tx) delay calibration.

Programmable hardware processing of the reset request bit in the CPRI frame.

Vendor-specific subchannel (VSS) communication on the CPRI link.

Diagnostic parallel reverse loopback paths.

Diagnostic stand-alone RE slave testing mode.

Includes the following additional interfaces:

Interface to external or on-chip processor, using the Altera Avalon

®

Memory-Mapped (Avalon-MM) interconnect specification.

Ethernet communication interfaces that support simultaneous Ethernet and
HDLC communication to and from the CPRI link.

Optional configuration of Ethernet MAC.

Optional Media-Independent Interface for Ethernet frame access.

Optional configuration of HDLC block.

Auxiliary interface provides full access to CPRI frame.

Supports data transfer to and from custom mapping functions, including
user-defined GSM mapping.

Supports data transfer from slave to master ports to implement daisy-chain
topologies.

Supports custom IQ sample widths.

Optional built-in IQ data interface with the following features:

Implements mapping methods in Sections 4.2.7.2.5 and 4.2.7.2.7 of the CPRI
V4.2 Specification, and mapping Options 1 and 2 in Sections 4.2.7.2.3 and
4.2.7.2.4 of the CPRI V4.2 Specification.

Implements WiMAX mapping methods described in Sections 4.2.7.2.2,
4.2.7.2.5, and 4.2.7.2.7 of the CPRI V4.2 Specification.

Implements UMTS/LTE mapping methods described in Section 4.2.7.2 of
the CPRI V4.2 Specification.

Implements WiMAX timing control methodology described in Section
4.2.8.2 of the CPRI V4.2 Specification.

Supports as many as 24 antenna-carrier interfaces.

Supports clocking antenna-carrier interfaces with external data channel
clocks or internal IP core clock.

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