Altera CPRI IP Core - Manual (Page 153)

Chapter 8: CPRI IP Core Demonstration Testbench 8–5
Running the Testbench
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
When frame synchronization completes, the value on the cpri_rx_state output port
(bits [1:0] of the extended_rx_status_data bus) is 0x3 and the value on the
cpri_rx_cnt_sync port (bits [4:2] of the extended_rx_status_data bus) is 0x1.
Following the appearance of these values, the value of the cpri_rx_hfn_state output
signal transitions to value 1, and then value of the cpri_rx_bfn_state output signal
transitions to value 1. When these values appear in the waveform display, the CPRI
link is up and ready to receive and send data.
Running the Testbench
This section describes how to run the CPRI IP core non-autorate negotiation
testbench. For information about how to run the autorate negotiation testbench, refer
to
Appendix C, CPRI Autorate Negotiation Testbench .
To run the CPRI IP core non-autorate negotiation testbench, perform the following
steps:
1. In the Quartus II software, create a project using the New Project Wizard on the
File menu.
2. Generate your CPRI IP core variation. When you are prompted to generate an
example design, you must turn on Generate Example Design and click Generate.
3. Close your Quartus II project.
4. Open the project <variation>_testbench/altera_cpri/generate_sim.qpf.
5. On the Tools menu, click Tcl Scripts and select generate_sim_verilog.tcl or
generate_sim_vhdl.tcl to generate a Verilog (.vo) or VHDL (.vho) simulation
model.
6. To compile and run the testbench, perform one of the following steps:
■ To compile and run the testbench using the Mentor Graphics ModelSim or
Aldec Riveria-PRO simulator, follow these steps:
i. Start a simulator session.
ii. In the simulator, change directory to the working directory subdirectory
< variation>_testbench/altera_cpri/cpri_testbench/<simulator>_sim.
iii. Type do compile.tcl
■ To compile and run the testbench using the Synopsys VCS or Cadence NCSIM
simulator, change directory to the working directory subdirectory
<
variation>_testbench/altera_cpri/cpri_testbench/<simulator>_sim and type
sh compile.sh .
The input to and subsequent output data from each of the AUX, mapN, and MI
interfaces is visible in the waveform for testbenches that have the relevant interface.