Altera CPRI IP Core - Manual (Page 160)

B–4 Appendix B: Implementing CPRI Link Autorate Negotiation
Autorate Negotiation From 9.8304 Gbps in Arria V GT Variations
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
2. Set the logic that feeds the gxb_refclk input to the CPRI IP core to the correct
value for the next CPRI line rate at which you want to try to achieve frame
synchronization.
3. Configure the ALTGX_RECONFIG megafunction, or the Altera Transceiver
Reconfiguration Controller for Arria V, Cyclone V, and Stratix V variations, with
the .mif file for the desired CPRI line rate. In Arria V, Cyclone V, and Stratix V
variations, alternatively, you can perform direct writes in streamer-based
reconfiguration mode.
4. For a Cyclone IV GX device, configure the ALTPLL_RECONFIG megafunction
with the .mif file for the desired CPRI line rate, by performing the following steps:
a. Assert the write_from_rom input signal to the ALTPLL_RECONFIG megafunction.
The megafunction busy output signal is asserted and remains asserted while
the megafunction writes to the scan cache.
b. After the megafunction busy output signal is deasserted, assert the
megafunction reconfig signal. While PLL reconfiguration is in progress, the
busy signal is again asserted.
c. After the CPRI IP core pll_reconfig_done signal is deasserted, assert the
megafunction reset_rom_address signal.
5. Set the i_datarate_set field of the AUTO_RATE_CONFIG register to the correct value
for the next CPRI line rate at which you want to try to achieve frame
synchronization.
6. Confirm the field is set by monitoring the datarate_set output signal.
7. Optionally, to enable confirmation of frame synchronization at the new CPRI line
rate, reset the tx_enable bit of the CPRI_CONFIG register to 0.
The frame synchronization machine shown in Figure 4–27 on page 4–56 attempts
to achieve frame synchronization at the specified CPRI line rate.
8. If you reset the tx_enable bit of the CPRI_CONFIG register in step 7 , after
extended_rx_status_data[1:0] changes value to 0x1, set the tx_enable bit of the
CPRI_CONFIG register.
The value 0x3 on the extended_rx_status_data[1:0] signal confirms that the
CPRI receiver has achieved frame synchronization.
Autorate Negotiation From 9.8304 Gbps in Arria V GT Variations
CPRI IP core variations that target an Arria V GT variation and that are configured
with the CPRI line rate of 9.8304 Gbps have additional requirements for autorate
negotiation.
In these variations, you must modify the frequency at which you drive the usr_clk
and usr_pma_clk input clocks to the IP core. The frequency depends on your target
CPRI line rate. These input clocks are not present in variations that target other
devices or that are configured in the CPRI parameter editor with different CPRI line
rates.