Altera CPRI IP Core - Manual (Page 117)

December 2013 Altera Corporation CPRI MegaCore Function
User Guide
7. Software Interface
The Altera CPRI IP core supports the following sets of registers that control the CPRI
IP core or query its status:
■ CPRI Protocol Interface Registers
■ MAP Interface and AUX Interface Configuration Registers
■ Ethernet Registers
■ HDLC Registers
All of the registers are 32 bits wide and their addresses are shown as hexadecimal
values. The registers can be accessed only on a 32-bit (4-byte) basis. The addressing for
the registers therefore increments by units of 4.
1 Reserved fields are labelled in the register tables. These fields are reserved for future
use and your design should not write to or rely on a specific value being found in any
reserved field or bit.
A remote device can access these registers only by issuing read and write operations
through the CPU interface.
Table 7–1 lists the access codes that describe the type of register bits.
Table 7–2 lists the CPRI IP core register address ranges.
Table 7–1. Register Access Codes
Code Description
RC Read to clear
RO Read-only
RW Read/write
UR0 Unused bits/read as 0
WO Write-only; read as 0
Table 7–2. CPRI IP Core Register Address Ranges
Address Range Interface
0x00–0x68 CPRI Protocol Interface Registers
0x100–0x1A4 MAP Interface and AUX Interface Configuration Registers
0xF4–0x1FC Reserved
0x200–0x24C Ethernet Registers
0x250–0x2FC Reserved
0x300–0x334 HDLC Registers