Altera CPRI IP Core - Manual (Page 182)

E–4 Appendix E: Delay Measurement and Calibration
Single-Hop Delay Measurement
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
The Rx path delay to the AUX interface or through the MAP interface module in most
CPRI IP core variations is the sum of the following delays:
1. The link delay is the delay between the arrival of the first bit of a 10 ms radio
frame on the CPRI Rx interface and the CPRI IP core internal transmission of the
radio frame pulse from the CPRI protocol interface receiver. The link delay
includes the following delays:
a. Rx transceiver latency is a fixed delay through the deterministic latency path of
the Rx transceiver. Its duration depends on the device family and the current
CPRI line rate. This delay includes comma alignment. Refer to
“Rx Transceiver
Latency” on the following pages.
b. Fixed delay from the Rx transceiver to the Rx elastic buffer. This delay depends
on the device family and CPRI data rate. This delay is the first component of
T_R1 in Figure E–1 on page E–2 . Refer to “Fixed Rx Core Delay Component” on
page E–7 .
c. Delay through the clock synchronization FIFO, as well as the phase difference
between the recovered receive clock and the core clock cpri_clkout . The
“Extended Rx Delay Measurement” section shows how to calculate the delay
in the CPRI Rx elastic buffer, which includes the phase difference delay.
d. Byte alignment delay that can occur as data is shifted out of the receiver. This
variable delay appears in the rx_byte_delay field of the CPRI_RX_DELAY
register—when the value in rx_byte_delay is non-zero, a byte alignment delay
of one cpri_clkout cycle occurs in the Rx path.
e. Variable delay introduced by round-trip delay calibration feature. Refer to
“Round-Trip Calibration Delay” on page E–7 and “Dynamic Pipelining for
Automatic Round-Trip Delay Calibration” on page E–19 .
2. Delay from the CPRI low-level receiver block to the AUX interface (or through the
MAP interface block). This delay depends on the device family and CPRI data
rate. This delay is the second component of
T_R1 in Figure E–1 on page E–2 . Refer
to “Fixed Rx Core Delay Component” on page E–7 .
Rx Path Delay Components
The CPRI specification defines requirements on the path to an SAP. The CPRI IP core
has one relevant SAP, the AUX interface. This section provides the information to
calculate the Rx path delay to output on the AUX interface.
The delay to—but not through—the AxC blocks, that is, the delay through the MAP
interface module, is the same as the delay to the AUX interface. The following sections
describe the Rx path delay components in the CPRI IP core variations.
Rx Transceiver Latency
The Altera high-speed transceiver is implemented using the deterministic latency
protocol, which ensures that delays in comma alignment and in byte alignment
within the transceiver are consistent.
In all CPRI IP core variations (except those that target an Arria V GT device and
are configured with the CPRI line rate of 9.8 Gbps), the delay through the Rx
transceiver is a fixed delay.