Altera CPRI IP Core - Manual (Page 144)

7–28 Chapter 7: Software Interface
HDLC Registers
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
0x32C HDLC_CONFIG_3 HDLC Feature Configuration 3
0x330 HDLC_CNT_RX_FRAME HDLC Receiver Module Frame Counter
0x334 HDLC_CNT_TX_FRAME HDLC Transmitter Module Frame Counter
Table 7–67. CPRI HDLC Registers Memory Map (Part 2 of 2)
Address Name Expanded Name
Table 7–68. HDLC_RX_STATUS—HDLC Receiver Module Status—Offset: 0x300
Field Bits Access Function Default
RSRV [31:7] UR0 Reserved. 25'h0
rx_ready_block [6] RO
Indicates that an eight-word block of HDLC data is available in the
HDLC Rx buffer to be transmitted on the HDLC channel.
1’h0
rx_ready_end [5] RO
Indicates the end-of-packet (EOP) is available in the HDLC Rx buffer,
ready to be transmitted on the HDLC channel.
1’h0
rx_length [4:3] RO
Length of the final word in the packet. Values are:
00: 1 valid byte
01: 2 valid bytes
10: 3 valid bytes
11: 4 valid bytes
2’h0
rx_abort [2] RO Indicates the current HDLC Rx packet is aborted. 1’h0
rx_eop [1] RO
Indicates that the next ready data word contains the end-of-packet
byte.
1’h0
rx_ready [0] RO
Indicates that at least one 32-bit word of HDLC data is available in the
HDLC Rx buffer.
1’h0
Table 7–69. HDLC_TX_STATUS—HDLC Transmitter Module Status—Offset: 0x304
Field Bits Access Function Default
RSRV [31:3] UR0 Reserved. 29'h0
tx_ready_block [2] RO
Indicates that the HDLC Tx module is ready to receive an 8-word block
of data.
1’h0
tx_abort [1] RO Indicates the current HDLC Tx packet is aborted. 1’h0
tx_ready [0] RO
Indicates that the HDLC Tx module is ready to receive at least one
32-bit word of data.
1’h0
Table 7–70. HDLC_CONFIG—HDLC Feature Configuration 1—Offset: 0x308 (Part 1 of 2)
Field Bits Access Function Default
RSRV [31:20] UR0 Reserved. 11'h0
intr_tx_ready_block_en [19] RW
Indicates an interrupt is generated when
tx_ready_block is asserted, if intr_en and
intr_tx_en are asserted.
1’h0
intr_tx_abort_en [18] RW
Indicates an interrupt is generated when tx_abort is
asserted, if intr_en and intr_tx_en are asserted.
1’h0
intr_tx_ready_en [17] RW
Indicates an interrupt is generated when tx_ready is
asserted, if intr_en and intr_tx_en are asserted.
1’h0