Altera CPRI IP Core - Manual (Page 217)

Additional InformationAdditional Information Info–5
Document Revision History
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
November 2011 11.1
■ Added support for Arria V and Stratix V devices.
■ Added information about new transceiver IP (the Altera Deterministic Latency PHY IP
core) in Arria V and Stratix V variations.
■ Added Tx elastic buffer and Tx extended delay measurement information.
■ Updated clocking diagrams with Tx elastic buffer and removal of divider on
transceiver-side clock before clocking Rx and Tx elastic buffers. Consolidated from six
figures to two.
■ Added information about new delay measurement features to enhance the consistency
of the round-trip delay through a CPRI RE slave: Tx bitslip, autocalibration.
■ Added new registers CPRI_TX_BITSLIP and CPRI_AUTO_CAL to support new features.
■ Removed use of the rx_byte_delay field in the CPRI_RX_DELAY register from the RX
path delay calculation.
■ Added new advanced Method 1 mapping mode and updated map_mode encodings.
■ Added new parameter to enable clocking AxC interfaces with cpri_clkout . The
resulting new synchronization mode requires a new signal, mapN_rx_start , per AxC
interface.
■ Added timing diagrams for three synchronization modes on MAP interface and for
cpri_tx_sync_rfp response behavior.
■ Added information about data order on the AUX interface.
■ Enhanced PRBS mode description.
■ Added Loopback Modes section in Functional Description chapter.
■ Updated Appendix C, Porting a CPRI IP Core from the Previous Version of the Software .
■ Refered to new What’s New in Altera IP page for information about IP core support level
for some device families.
May 2011 11.0
■ Upgraded to final support for Arria II GZ and Cyclone IV GX devices.
■ Upgraded to HardCopy Compilation support for HardCopy IV GX devices.
■ Added byte-enable signal.
■ Added parameter to control WIDTH_RX_BUF.
■ Enhanced delay measurement and cpri_tx_sync_rfp signal descriptions.
■ Modified MII and frame synchronization machine descriptions.
■ Miscellaneous small fixes, including:
■ Updated address range for MAP and AUX interface configuration registers in
Table 6–2 on page 6–1 to match individual register addresses as updated for v10.1.
■ Updated descriptions of frame synchronization machine and cpri_rx_cnt_sync
signal.
■ Added Appendix C, Porting a CPRI IP Core from the Previous Version of the Software .
Date Version Changes Made