Altera CPRI IP Core - Manual (Page 8)

1–2 Chapter 1: About This MegaCore Function
General Description
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
General Description
The Altera CPRI IP core implements Layer 1 and Layer 2 of the CPRI V5.0
specification. It provides access to the V5.0 Layer 1 and Layer 2 access points through
various interfaces:
■ V5.0 Layer 1 access:
■ Auxiliary (AUX) interface for full access to V5.0 control data stream for
antenna-carrier (Ctrl_AxC) bytes in control word.
■ Register support for loading and unloading full control words, including
Ctrl_AxC bytes.
■ Auxiliary (AUX) interface support for user-defined GSM mapping.
■ IQ data access:
■ Mapping block (MAP) to antenna-carrier interfaces for easy IQ user data plane
access based on pre-configured antenna-carrier channels.
■ Auxiliary (AUX) interface for full access to the user data plane.
■ Ethernet channel access:
■ Auxiliary interface for full access to the Ethernet space in the CPRI frame.
■ Register support for loading and unloading the Ethernet frame.
■ Media independent (MI) interface port for Ethernet Frame access.
■ High level data link control (HDLC) channel access:
■ Auxiliary interface for full access to the HDLC space in the CPRI frame.
■ Register support for loading and unloading the HDLC frame.
■ Vendor-specific space (VSS) data:
■ Auxiliary interface for full access to control words.
■ Register support for loading and unloading full control words, including VSS
space.
■ Synchronization and timing access:
■ Auxiliary interface for full access to synchronization and timing.
You configure the CPRI IP core to include an Ethernet media access control (MAC)
block or to communicate with an external Ethernet module through an MI interface.
You can configure the CPRI link line rate.
For information about the CPRI IP core interfaces and functionality, refer to Chapter 4,
Functional Description . For information about configuration options, refer to
Chapter 3, Parameter Settings .