Altera CPRI IP Core - Manual (Page 70)

4–38 Chapter 4: Functional Description
Media Independent Interface to an External Ethernet Block
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
MII Transmitter
The MII transmitter module receives data from the external Ethernet MAC block and
writes it to the CPRI transmitter module, which transmits it on the CPRI link. It
performs 4B/5B encoding on the incoming data nibbles before sending them to the
CPRI transmitter module.
After the CPRI IP core achieves frame synchronization, the MII transmitter module
can accept incoming data on the MII. The MII transmitter module asserts the
cpri_mii_txrd signal to indicate it is ready to accept data from the external Ethernet
MAC block. After the cpri_mii_txrd signal is asserted, the external Ethernet block
asserts the cpri_mii_txen signal to indicate it is ready to provide data. The MII
transmitter module deasserts the cpri_mii_txrd signal in the cycle following each
cycle in which it receives data. It may remain deasserted for multiple cycles, to
prevent buffer overflow. While the
cpri_mii_txrd signal remains low, the external
Ethernet block must maintain the data value on cpri_mii_txd .
During the first cpri_mii_txclk cycle in which cpri_mii_txen is asserted, the MII
module inserts an Ethernet J symbol (5’b11000) in the buffer of data to be transmitted
to the CPRI link; during the second cycle in which
cpri_mii_txen is asserted, the MII
module inserts an Ethernet K symbol (5’b10001) in this buffer. These two symbols
indicate Ethernet start-of-packet. While the CPRI MII transmitter is inserting the J and
K symbols, it ignores incoming data on
cpri_mii_txd . Refer to Figure 4–22 .
Typically, the external Ethernet block asserts cpri_mii_txen one clock cycle after
cpri_mii_txrd is asserted. While the cpri_mii_txen signal remains asserted, the MII
transmitter module reads data on the cpri_mii_txd input data bus. Following this
data sequence, in the first two cpri_mii_txclk cycles in which the cpri_mii_txen
signal is not asserted, the MII module inserts an Ethernet end-of-packet symbol—T
followed by R. While the CPRI MII transmitter is inserting the T and R symbols, it
ignores incoming data on
cpri_mii_txd . Refer to Figure 4–22 .
While cpri_mii_txen is asserted, the cpri_mii_txer input signal indicates that the
current nibble on cpri_mii_txd is suspect. Therefore, if the MII transmitter module
observes that both cpri_mii_txen and cpri_mii_txer are asserted in the same
cpri_mii_txclk cycle, the MII module inserts an Ethernet HALT symbol (5’b00100).
Figure 4–24 on page 4–41 provides an example in which the cpri_mii_txer signal is
asserted, and shows how the error indication propagates to the MII receiver module
on the CPRI link slave.