High-speed transceiver, Rx elastic buffer, High-speed transceiver –54 rx elastic buffer –54 – Altera CPRI IP Core User Manual
Page 86: Fer to, Rx elastic buffer” on
4–54
Chapter 4: Functional Description
CPRI Protocol Interface Layer (Physical Layer)
CPRI MegaCore Function
December 2013
Altera Corporation
User Guide
■
Separates data for the MAP interface block, the AUX module, the Ethernet MAC
block or the MII module, and the HDLC module.
■
Detects loss of signal (LOS), loss of frame (LOF), remote alarm indication (RAI),
and service access point (SAP) defect indication (SDI) errors
High-Speed Transceiver
The high-speed transceiver on the CPRI IP core CPRI protocol interface is configured
with the Altera ALTGX megafunction in Arria II, Cyclone IV GX, and Stratix IV GX
devices, with the Altera Deterministic Latency PHY IP core in Arria V, Cyclone V, and
Stratix V GX devices and in some variations in Stratix V GT devices, and with the
Altera Native PHY IP core in variations with a CPRI line rate of 9830.4 Mbps in
Stratix V GT devices.
The transceiver receiver implements 8B/10B decoding and the deterministic latency
protocol. The deterministic latency protocol is designed to meet the 16.276 ns
round-trip delay measurement accuracy requirements R21 and R21A of the CPRI
specification.
f
For information about the high-speed transceiver blocks, refer to
of the
Arria II Device Handbook, to
of the Cyclone IV Device Handbook, or to
and
of the Stratix IV Device Handbook.
f
For information about the Altera Deterministic Latency PHY IP core and the Altera
Native PHY IP core, refer to the
.
Rx Elastic Buffer
The low-level interface receiver converts data from the transceiver clock domain and
data width to the main CPRI IP core clock domain and data width using a
synchronization FIFO called the Rx elastic buffer. The Rx elastic buffer data output is
clocked with the
cpri_clkout
clock. The Rx elastic buffer data input is synchronous
with the
rx_clkout
clock from the transceiver. The width of an Rx elastic buffer entry
is 32 bits, and the
rx_clkout
clock clocks the transceiver data, which is 8, 16, or 32 bits
wide. For details, refer to
“Clock Diagrams for the CPRI IP Core” on page 4–5
The default depth of the Rx elastic buffer is 64 32-bit entries. For most systems, the
default Rx elastic buffer depth is adequate to handle dispersion, jitter, and wander
that can occur on the link while the system is running. However, the Receiver buffer
depth
parameter is available for cases in which additional depth is required.
1
Altera recommends that you set Receiver buffer depth to 4 in CPRI RE slave
variations, specifying a depth of 16 32-bit entries.
You must realign and resynchronize the Rx elastic buffer after a dynamic CPRI line
rate change. Resynchronizing the Rx elastic buffer resets its pointers. Program the
CPRI_RX_DELAY_CTRL
register to realign and resynchronize the Rx elastic buffer.
The Rx elastic buffer adds variable delay to the Rx path through the CPRI IP core.
Refer to