Altera CPRI IP Core - Manual (Page 190)

E–12 Appendix E: Delay Measurement and Calibration
Single-Hop Delay Measurement
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
Table E–5 shows the sum of these two fixed delays for Arria V GT 9.8 Gbps
variations.
Round-Trip Calibration Delay
The new dynamic pipelining feature for round-trip delay calibration introduces a
delay in the Rx path in an RE slave. In the Arria V GT 9.8 Gbps variations, this
delay is introduced in the CPRI Rx block.
f For more information about this feature, refer to “Dynamic Pipelining for
Automatic Round-Trip Delay Calibration” on page E–19 and to Table 7–29
on page 7–14 .
Tx Path Delay
The Tx path delay is the cumulative delay from the arrival of the first bit of a 10 ms
radio frame on the CPRI AUX interface to the start of transmission of this data on the
CPRI link. This section provides the information to calculate the Tx path delay. The
following sections describe the delay for the following variations:
■ Most CPRI IP Core Variations
■ Arria V GT 9.8 Gbps
Most CPRI IP Core Variations
The delay through the MAP interface module to the CPRI link is the same as the delay
from the AUX interface. The following sections describe the Tx path delay
components in the CPRI IP core variations.
Tx Path Delay Components
The delay through the MAP interface module to the CPRI link is the same as the delay
from the AUX interface. The following sections describe the Tx path delay
components in the CPRI IP core variations.
Table E–5. Fixed Latency T_R1 in cpri_clkout Cycles
CPRI Line Rate
(Gbps)
Latency Through Core on Rx Path in cpri_clkout Clock Cycles
Arria V GT Device Configured at 9.8304 Gbps
9.8304 4