Altera CPRI IP Core - Manual (Page 196)

E–18 Appendix E: Delay Measurement and Calibration
Single-Hop Delay Measurement
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
Variable Delay through Tx Buffer
This delay is the extended Tx delay. The calculation is the same as for the Rx
extended delay measurement.
Toffset
Use the following formula to calculate the Toffset delay:
Toffset = <RE Rx path delay> + <RE Tx path delay> + <loopback delay>
where <loopback_delay> is listed in Table E–8 .
Table E–8 provides the loopback delay in cpri_clkout clock cycles for various
combinations of devices and data rates.
Round-Trip Delay
The rx_round_trip_delay field of the CPRI_ROUND_DELAY register records the total
round-trip delay from the start of the internal transmit radio frame in the REC to the
start of the internal receive radio frame in the REC, that is, from SAP to SAP. The
register value is only available in CPRI REC and RE masters.
CPRI V5.0 Specification requirements R-20 and R-21 address the round-trip delay.
Requirement R-20 addresses the measurement without including the cable delay, and
requirement R-21 is the requirement for the cable delay. Both requirements state that
the variation must be no more than ±16.276 ns.
The CPRI IP core supports two approaches to these requirements. In the first
approach, you perform calculations based on register values to determine the current
delay, and check periodically to confirm that the variation in measurements over time
is small enough that the requirements are met.
In the second approach, you activate the new dynamic pipelining feature to perform
round-trip delay calibration. This feature enables the CPRI IP core to compensate
dynamically for variations from a predetermined round-trip delay value that you
select.
Round-Trip Cable Delay
The round-trip cable delay is the sum of T12 and T34 (refer to Figure E–1 on
page E–2 ). The CPRI V5.0 Specification requirement R-21 requires that we ensure an
accuracy of ±16.276 ns in the measurement of the round-trip cable delay in a
single-hop configuration.
Table E–8. Loopback Delay (cpri_clkout Clock Cycles)
Family Data Rate Delay
Arria V GX 4.9152, 6.144, 9.8304 6
Arria V GT 4.9152, 6.144, 9.8304 6
Arria V GZ 6.144, 9.8304 6
Stratix V 6.144, 9.8304 6
All other combinations 1