Altera CPRI IP Core - Manual (Page 207)

December 2013 Altera Corporation CPRI MegaCore Function
User Guide
F. Integrating the CPRI IP Core Timing
Constraints in the Full Design
When you generate your CPRI IP core variation, the Quartus II software generates a
Synopsys Design Constraints File (.sdc) that specifies the timing constraints for the
input clocks to your IP core. At the time you generate the CPRI IP core, your design is
not yet complete and the CPRI IP core is not yet connected in the design. The final
clock names and paths are not yet known, and therefore the Quartus II software
cannot incorporate the final signal names in the .sdc file it generates automatically.
Instead, you must modify the clock signal names in this file manually to integrate
these constraints with the timing constraints for your full design.
This appendix describes by example how to integrate the timing constraints that the
Quartus II software generates with your CPRI IP core into the timing constraints for
your design.
For a list of the input clocks to the CPRI IP core, refer to Table 4–1 on page 4–3 .
In the Quartus II software release v12.0 and later, the automatically generated
altera_cpri.sdc
file contains the CPRI IP core timing constraints.
For a CPRI IP core with a single antenna-carrier interface that runs at the CPRI line
rate of 3.072 Gbps and targets an Arria II GX device, the Quartus II software v12.0
generates an altera_cpri.sdc file with the following timing constraints:
#ALTGX Transceiver Reference Clock
create_clock -name gxb_refclk -period 6.510 -waveform {0.000 3.255} [get_ports
gxb_refclk]
#Clock from Clean-Up PLL (RE slave only)
create_clock -name gxb_pll_inclk -period 6.510 -waveform {0.000 3.255} [get_ports
gxb_pll_inclk]
#ALTGX Calibration Block Clock (10MHz to 125 MHz)
create_clock -name gxb_cal_blk_clk -period 8.000 -waveform {0.000 4.000}
[get_ports gxb_cal_blk_clk]
#ALTGX_RECONFIG Clock (37.5MHz to 50MHz)
create_clock -name reconfig_clk -period 20.000 -waveform {0.000 10.000}
[get_ports reconfig_clk]
#CPRI CPU Clock
create_clock -name cpu_clk -period 32.552 -waveform {0.000 16.276} [get_ports
cpu_clk]
#Extended Delay Measurement Clock
create_clock -name clk_ex_delay -period 13.123 -waveform {0.000 6.562} [get_ports
clk_ex_delay]
#Data Mapping Clock
create_clock -name map0_tx_clk -period 260.416 -waveform {0.000 130.208}
[get_ports map0_tx_clk]
create_clock -name map0_rx_clk -period 260.416 -waveform {0.000 130.208}
[get_ports map0_rx_clk]
derive_pll_clocks
derive_clock_uncertainty