Altera CPRI IP Core - Manual (Page 91)

Chapter 4: Functional Description 4–59
CPRI Protocol Interface Layer (Physical Layer)
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
Scrambling
When the tx_prot_version field of the CPRI_TX_PROT_VER register ( Table 7–25 on
page 7–12 ) holds the value 2, the low-level CPRI transmitter scrambles the data words
according to the CPRI V5.0 Specification, using the seed in the tx_scr_seed field of
the CPRI_TX_SCR_SEED register ( Table 7–26 on page 7–13 ).
Tx Elastic Buffer
The low-level interface transmitter converts data from the main CPRI IP core clock
domain and data width to the transceiver clock domain and data width using a
synchronization FIFO called the Tx elastic buffer. The Tx elastic buffer data input is
clocked with the
cpri_clkout clock, and the buffer data output is clocked with the
tx_clkout clock from the transceiver. Data in the Tx elastic buffer is 32 bits wide, and
the data bus to the transceiver is 8, 16, or 32 bits wide, depending on the target device
family and the CPRI line rate. The CPRI IP core derives the
cpri_clkout clock from
the Tx output clock of the transceiver, divided as necessary to support the data width
conversion to and from the 32-bit wide elastic buffers.
Table 4–17 shows the data bus
widths and clock divisors for the different device families and CPRI line rates.
High-Speed Transceiver
The high-speed transceiver on the CPRI IP core CPRI protocol interface is configured
with the Altera ALTGX megafunction in Arria II, Cyclone IV GX, and Stratix IV GX
devices, with the Altera Deterministic Latency PHY IP core in ArriaV, Cyclone V, and
Stratix V GX devices and in some variations in Stratix V GT devices, and with the
Altera Native PHY IP core in variations with a CPRI line rate of 9830.4 Mbps in
Stratix V GT devices.
The transceiver transmitter implements 8B/10B encoding and the deterministic
latency protocol. It transforms the 16-bit parallel input data to the Arria II GX or
Cyclone IV GX transmitter, or 32-bit parallel input data to the Arria II GZ, Arria V,
Stratix IV GX, or Stratix V transmitter, to 8-bit data before 8B/10B encoding. The 10-
bit encoded data is then serialized and sent to the CPRI link differential output pins.
The deterministic latency protocol is designed to meet the 16.276-ns round-trip delay
measurement accuracy requirements R21 and R21A of the CPRI specification.
Table 4–17. Transceiver Datapath Width and tx_clkout Divider
CPRI Line Rate
(Mbps)
Device Family (1)
Transceiver Datapath Width
(Bits)
tx_clkout Divider
614.4 All 8 4
Greater than 614.4
Arria II GX, Cyclone IV GX 16 2
Arria II GZ, Arria V,
Cyclone V, Stratix IV GX, and
Stratix V
32 1
Note to Table 4–17 :
(1) Arria V GT devices that target 9.830 Gbps do not have a tx_clkout divider after auto-rate negotiations. cpri_clkout is derived directly from
the input clock usr_clk . The TX elastic buffer synchronizes between the transceiver PMA clock out and the user-derived clock usr_clk (or
cpri_clkout ).