Document Outline

• Section I – Technology
  • DOCUMENT ORGANIZATION
  • DOCUMENT HISTORY
  • CONTENTS
  • TABLES
  • FIGURES
  • ABBREVIATIONS
• 1 EtherCAT Slave Controller Overview
  • 1.1 EtherCAT Slave Controller Function Blocks
  • 1.2 Further Reading on EtherCAT and ESCs
  • 1.3 Scope of Section I
• 2 EtherCAT Protocol
  • 2.1 EtherCAT Header
  • 2.2 EtherCAT Datagram
  • 2.3 EtherCAT Addressing Modes
    • 2.3.1 Device Addressing
    • 2.3.2 Logical Addressing
  • 2.4 Working Counter
  • 2.5 EtherCAT Command Types
• 3 Frame Processing
  • 3.1 Loop Control and Loop State
  • 3.2 Frame Processing Order
  • 3.3 Permanent Ports and Bridge Port
  • 3.4 Shadow Buffer for Register Write Operations
  • 3.5 Circulating Frames
    • 3.5.1 Unconnected Port 0
  • 3.6 Non-EtherCAT Protocols
  • 3.7 Special Functions of Port 0
• 4 Physical Layer Common Features
  • 4.1 Link Status
  • 4.2 Selecting Standard/Enhanced Link Detection
  • 4.3 FIFO Size Reduction
  • 4.4 Frame Error Detection
• 5 Ethernet Physical Layer
  • 5.1 Requirements to Ethernet PHYs
  • 5.2 PHY reset and Link partner notification/loop closing
  • 5.3 MII Interface
  • 5.4 RMII Interface
  • 5.5 RGMII Interface
    • 5.5.1 RGMII In-Band Link Status
  • 5.6 Link Detection
    • 5.6.1 LINK_MII Signal
    • 5.6.2 MI Link Detection and Configuration
  • 5.7 Standard and Enhanced MII Link Detection
  • 5.8 EtherCAT over Optical Links (FX)
    • 5.8.1 Link partner notification and loop closing
    • 5.8.2 Far-End-Fault (FEF)
    • 5.8.3 ESCs with native FX support
    • 5.8.4 ESCs without native FX support
  • 5.9 Gigabit Ethernet PHYs
  • 5.10 MII Management Interface (MI)
    • 5.10.1 PHY Addressing/PHY Address Offset
    • 5.10.2 Logical Interface
      • 5.10.2.1 MI read/write example
      • 5.10.2.2 MI Interface Assignment to ECAT/PDI
    • 5.10.3 MI Protocol
    • 5.10.4 Timing specifications
  • 5.11 MII management example schematic
  • 5.12 Ethernet Termination and Grounding Recommendation
  • 5.13 Ethernet Connector (RJ45 / M12)
  • 5.14 Back-to-Back MII Connection
    • 5.14.1 ESC to ESC Connection
    • 5.14.2 ESC to Standard Ethernet MAC
• 6 EBUS/LVDS Physical Layer
  • 6.1 Interface
  • 6.2 EBUS Protocol
  • 6.3 Timing Characteristics
  • 6.4 Standard EBUS Link Detection
  • 6.5 Enhanced EBUS Link Detection
  • 6.6 EBUS RX Errors
  • 6.7 EBUS Low Jitter
  • 6.8 EBUS Connection
• 7 FMMU
• 8 SyncManager
  • 8.1 Buffered Mode
  • 8.2 Mailbox Mode
    • 8.2.1 Mailbox Communication Protocols
  • 8.3 PDI register function acknowledge by Write
  • 8.4 Interrupt and Watchdog Trigger Generation, Latch Event Generation
  • 8.5 Single Byte Buffer Length / Watchdog Trigger for Digital Output PDI
  • 8.6 Repeating Mailbox Communication
  • 8.7 SyncManager Deactivation by the PDI
• 9 Distributed Clocks
  • 9.1 Clock Synchronization
    • 9.1.1 Clock Synchronization Process
    • 9.1.2 Propagation Delay Measurement
      • 9.1.2.1 Propagation Delay Measurement in Reverse Mode
      • 9.1.2.2 Propagation Delay Measurement Example
    • 9.1.3 Offset Compensation
    • 9.1.4 Resetting the Time Control Loop
    • 9.1.5 Drift Compensation
    • 9.1.6 Reference between DC Registers/Functions and Clocks
    • 9.1.7 When is Synchronization established?
    • 9.1.8 Clock Synchronization Initialization Example
  • 9.2 SyncSignals and LatchSignals
    • 9.2.1 Interface
    • 9.2.2 Configuration
    • 9.2.3 SyncSignal Generation
      • 9.2.3.1 Cyclic Generation
      • 9.2.3.2 Single Shot Mode
      • 9.2.3.3 Cyclic Acknowledge Mode
      • 9.2.3.4 Single Shot Acknowledge Mode
      • 9.2.3.5 SYNC1 Generation
      • 9.2.3.6 SyncSignal Initialization Example
    • 9.2.4 LatchSignals
      • 9.2.4.1 Single Event Mode
      • 9.2.4.2 Continuous Mode
      • 9.2.4.3 SyncManager Event
    • 9.2.5 ECAT or PDI Control
  • 9.3 System Time PDI Controlled
  • 9.4 Communication Timing
• 10 EtherCAT State Machine
  • 10.1 EtherCAT State Machine Registers
    • 10.1.1 AL Control and AL Status Register
    • 10.1.2 Device Emulation
    • 10.1.3 Error Indication and AL Status Code Register
• 11 SII EEPROM
  • 11.1 SII EEPROM Content
  • 11.2 SII EEPROM Logical Interface
    • 11.2.1 SII EEPROM Errors
      • 11.2.1.1 Missing Acknowledge
    • 11.2.2 SII EEPROM Interface Assignment to ECAT/PDI
    • 11.2.3 Read/Write/Reload Example
    • 11.2.4 EEPROM Emulation
  • 11.3 SII EEPROM Electrical Interface (I2C)
    • 11.3.1 Addressing
    • 11.3.2 EEPROM Size
    • 11.3.3 I²C Access Protocol
      • 11.3.3.1 Write Access
      • 11.3.3.2 Read Access
    • 11.3.4 Timing specifications
• 12 Interrupts
  • 12.1 AL Event Request (PDI Interrupt)
  • 12.2 ECAT Event Request (ECAT Interrupt)
  • 12.3 Clearing Interrupts Accidentally
• 13 Watchdogs
  • 13.1 Process Data Watchdog
  • 13.2 PDI Watchdog
• 14 Error Counters
  • 14.1 Frame error detection
  • 14.2 Errors and Forwarded Errors
• 15 LED Signals (Indicators)
  • 15.1 RUN LED
    • 15.1.1 RUN LED override
  • 15.2 ERR LED
    • 15.2.1 ERR LED override
  • 15.3 STATE LED and STATE_RUN LED Signal
  • 15.4 LINKACT LED
  • 15.5 Port Error LED (PERR)
• 16 Process Data Interface (PDI)
  • 16.1 PDI Selection and Configuration
  • 16.2 PDI register function acknowledge by write
  • 16.3 General Purpose I/O
    • 16.3.1 General Purpose Inputs
    • 16.3.2 General Purpose Output
• 17 Additional Information
  • 17.1 ESC Clock Source
  • 17.2 Power-on Sequence
  • 17.3 Write Protection
    • 17.3.1 Register Write Protection
    • 17.3.2 ESC Write Protection
  • 17.4 ESC Reset
• 18 Appendix
  • 18.1 Support and Service
    • 18.1.1 Beckhoff’s branch offices and representatives
  • 18.2 Beckhoff Headquarters