Altera Arria 10 Avalon-MM DMA - Manual (Page 111)

The Hard IP block implements data poisoning, a mechanism for indicating that the data associated with a
transaction is corrupted. Poisoned TLPs have the error/poisoned bit of the header set to 1 and observe the
following rules:
• Received poisoned TLPs are sent to the Application Layer and status bits are automatically updated in
the Configuration Space.
• Received poisoned Configuration Write TLPs are not written in the Configuration Space.
• The Configuration Space never generates a poisoned TLP; the error/poisoned bit of the header is
always set to 0.
Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.
Table 8-5: Parity Error Conditions
Status Bit Conditions
Detected parity error (status register bit 15) Set when any received TLP is poisoned.
Master data parity error (status register bit 8) This bit is set when the command register parity
enable bit is set and one of the following conditions
is true:
• The poisoned bit is set during the transmission
of a Write Request TLP.
• The poisoned bit is set on a received completion
TLP.
Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit
TLPs are similarly sent to the link.
Related Information
PCI Express Base Specification 3.0
Uncorrectable and Correctable Error Status Bits
The following section is reprinted with the permission of PCI-SIG. Copyright 2010 PCI-SIG.
8-6 Uncorrectable and Correctable Error Status Bits
UG-01145_avmm_dma
2015.05.14
Altera Corporation Error Handling
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