Altera Arria 10 Avalon-MM DMA - Manual (Page 130)

Date Version Changes Made
• Corrected Reset Controller in Arria 10 Devices figure in Reset and
Clocks chapter.
• Corrected bit definitions for
CvP Status
register.
• Removed PLL from channel placement figures.
• Added fast passive parallel (FPP) to supported configuration
schemes in CvP in Arria 10 Devices figure.
• Updated Power Supply Voltage Requirements table.
• Corrected the name of the Descriptor Instructions bus. The letters
DMA are now Ast. For example
WrDMARXValid_i
is now
WrAstRXValid_i
.
• Added
RD_CONTROL
and
WR_CONTROL
register
Done
bit. When set,
the Descriptor Controller writes this bit for each descriptor in the
status table and sends a single MSI interrupt after the final
descriptor completes.
• Removed the following chapters that have minimal relevance to
the Arria 10 Avalon-MM DMA Interface IP Core. These chapters
are available in the more comprehensive Avalon-ST versions :
• Design Implementation
• Optional Features
• Debugging
• Throughput Optimization
2013.12.02 13.1 Arria 10
Initial release.
How to Contact Altera
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Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training
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Email [email protected]
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B-4 How to Contact Altera
UG-01145_avmm_dma
2015.05.14
Altera Corporation Additional Information
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